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Laura Peters

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Laura Peters is senior executive editor for manufacturing and test at Semiconductor Engineering.

Author's Latest Posts

Identifying Sources Of Silent Data Corruption
By Laura Peters - 08 May, 2025 - Comments: 0

Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets. ... » read more

Backside Power Delivery Nears Production
By Laura Peters - 17 Apr, 2025 - Comments: 0

Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling. It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern di... » read more

Why Thin Film Measurements Matter
By Laura Peters - 08 Apr, 2025 - Comments: 0

Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

The Rise Of Thin Wafer Processing
By Laura Peters - 20 Mar, 2025 - Comments: 0

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a ... » read more

Automation And AI Improve Failure Analysis
By Laura Peters - 11 Mar, 2025 - Comments: 0

When a chip malfunctions it’s the job of the failure analysis engineer to determine how it failed or significantly deviated from its key performance metrics. The cost of failure in the field can be huge in terms of downtime, recalls, damage to a company’s reputation, and more. For these reasons, chipmakers take customer returns very seriously, focusing resources to quickly get to the bot... » read more

Interconnects Approach Tipping Point
By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Silent Data Errors Still Slipping Through The Cracks
By Laura Peters - 11 Feb, 2025 - Comments: 0

Silent data corruption errors in large server farms have become a major concern of cloud users, hyperscalers, processor manufacturers and the test community. Silent data errors (also called silent data corruption errors) are hardware errors that occur when an incorrect computational result from a processor core goes undetected by the system. The data is silently corrupted because neither sof... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Silicon Lifecycle Management Gains Steam
By Laura Peters - 10 Dec, 2024 - Comments: 0

Silicon lifecycle management (SLM) is gaining significant traction, driven increasingly by stringent reliability requirements for safety-critical devices in aerospace, medical, and automotive. Improving reliability has been a discussion point for years, but it has become especially important with the use of chips designed at leading-edge nodes in both mission- and safety-critical application... » read more

HBM Options Increase As AI Demand Soars
By Laura Peters - 21 Nov, 2024 - Comments: 0

High-bandwidth memory (HBM) sales are spiking as the amount of data that needs to be processed quickly by state-of-the-art AI accelerators, graphic processing units, and high-performance computing applications continues to explode. HBM inventories are sold out, driven by massive efforts and investments in developing and improving large language models such as ChatGPT. HBM is the memory of ch... » read more

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