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Power Intent Formats: Isolation
By Luke Lang - 03 Nov, 2011 - Comments: 0

By Luke Lang Last month, I discussed power domain for all three power formats: CPF, UPF 1.0, and IEEE 1801. I mentioned isolation but mainly used it to explain power domain. This month’s blog will address isolation in detail. First, isolation cells are required at off-to-on domain crossings. When a domain is shut off, all of its output nets become undriven. If these floating nets drive direct... » read more

Power Intent Formats: Power Domain
By Luke Lang - 06 Oct, 2011 - Comments: 0

By Luke Lang Starting this month, I will be writing a series of blogs inspired by “Dueling Power Formats”. The article correctly points out that there are currently three power formats: CPF, UPF 1.0, and IEEE 1801. Some designers will find themselves in a position of having to choose a format. Others will need to work with both formats. Regardless of which position one is in, these LP desi... » read more

Hierarchical LP Design 3
By Luke Lang - 08 Sep, 2011 - Comments: 0

By Luke Lang Last month, I wrote in favor of top-down approach to coding the power intent. This month, let’s take a look at the bottom-up approach. With the top-down approach, we code the full-chip power intent without having to worry about all the nets that cross power domain boundaries. Then we issue a few commands, and a tool writes out the block-level CPF. Pretty simple and straightfo... » read more

Hierarchical LP Design 2
By Luke Lang - 11 Aug, 2011 - Comments: 0

By Luke Lang Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to describe the power intent and drive the tools. Without these commands, it is extremely difficult to do hierarchical design. But with these commands, hierarchical power intent files are n... » read more

Hierarchical LP Design
By Luke Lang - 21 Jul, 2011 - Comments: 0

By Luke Lang The rapidly shrinking process geometry is a double-edged sword. It allows unprecedented integration of circuits. But it also produces leakier transistors, which is one of the main reasons behind the need for low-power design techniques. Therefore, a good low-power design flow must not only automate low-power design, verification, and implementation, it must also support hierarchic... » read more

Low Power Simulation
By Luke Lang - 16 Jun, 2011 - Comments: 0

By Luke Lang Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading. In order to run VDD/VSS-aware simulation, one must ha... » read more

The Real Value Of An LP Methodology
By Luke Lang - 12 May, 2011 - Comments: 0

By Luke Lang “What are some of the low-power mistakes that you have seen?” That is, by far, the most popular question asked by designers. And it’s a very good question. Why re-invent the wheel? Why repeat mistakes? It’s a lot easier to learn from someone else’s mistakes than from your own. Clearly, every company is different, and every design is different. But there are lots of co... » read more

RTL Power Estimation
By Luke Lang - 14 Apr, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estim... » read more

Fast LP Simulation
By Luke Lang - 17 Mar, 2011 - Comments: 0

By Luke Lang What are the most important features of a logic simulator? I’m sure there have been lots of surveys done for this question. Unfortunately, I can’t find any results on Google. Nevertheless, I would be willing to bet that fast performance is at or near the top of every verification engineer’s wish list. For the low-power verification engineers, fast performance is also a ke... » read more

Golden Power Intent
By Luke Lang - 13 Jan, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about the rapid adoption of the power intent file for low-power designs. While this is certainly a step in the right direction, some design teams may be taking several steps backwards by not treating the power intent file with the proper respect. For example, I have seen one case where the verification, synthesis, and backend implementation teams each had... » read more

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