Author's Latest Posts

The Criticality Of The E/E Architecture
By Mentor, a Siemens Business - 04 Mar, 2020 - Comments: 0

Modern vehicles are highly sophisticated systems incorporating electrical, electronic, software and mechanical components. Mechanical systems are giving way to advanced software and electronic devices, driving automakers to innovate and differentiate their vehicles via the electric and electronic (E/E) architecture. Future architectures need to be scalable across vehicle platforms, flexible to ... » read more

Parasitic Extraction of MIM/MOM Capacitors In Analog/RF Designs
By Mentor, a Siemens Business - 26 Feb, 2020 - Comments: 0

The extensive use of MIM/MOM capacitors in analog/RF designs presents designers with extraction challenges that typically require multiple extraction techniques. The Calibre xACT platform offers analog/RF designers the fast performance of a rule-based extraction engine, and the capacity and performance of a field solver, to efficiently extract all parasitic components in a timely manner, with t... » read more

Interconnect Inductance Extraction For Analog And RF IC Designs
By Mentor, a Siemens Business - 12 Feb, 2020 - Comments: 0

Increasing operating frequencies for analog/RF designs mean interconnect inductance parasitic extraction is now required to ensure accurate circuit performance and high reliability. Automated field solver-based inductance extraction of both self and mutual parasitics enables IC companies to deliver analog/RF chips that provide the intended level of performance and reliability. To read more, ... » read more

Optimal End-to-End DFT Automation With Tessent Connect
By Mentor, a Siemens Business - 11 Feb, 2020 - Comments: 0

With the growth in design size and complexity, DFT engineers began adopting new methods to reduce DFT implementation time, reduce test costs, and reduce risks to design schedules by removing DFT from the critical path to tapeout. The primary method to accomplish large improvements to DFT efficiency is through a divide-and-conquer approach supported by Tessent’s RTL-based, hierarchical DFT ins... » read more

Push-Button FMEDAs for Automotive Safety
By Mentor, a Siemens Business - 05 Feb, 2020 - Comments: 0

Automotive designs require functional safety analysis, typically accomplished using Failure Modes, Effects and Diagnostic Analysis (FMEDA), used to determine each safety goal’s diagnostic coverage. Writing an FMEDA is a highly tedious task, so we share a push-button solution for creating and automating the FMEDA process, giving engineers more time to focus on exploring design safety readiness... » read more

Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking
By Mentor, a Siemens Business - 29 Jan, 2020 - Comments: 0

A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

Random Directed Low Power Coverage Methodology
By Mentor, a Siemens Business - 15 Jan, 2020 - Comments: 0

This paper proposes a low-power coverage methodology based on the recently introduced UPF 3.0 low-power information model HDL package. Verification engineers can use this approach to achieve low-power coverage closure earlier. We share relevant case studies and examples using the methodology to solve low-power verification problems. It also discusses the benefits of this approach and its advant... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology
By Mentor, a Siemens Business - 14 Jan, 2020 - Comments: 0

This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Using Hypervisor For IVI And AUTOSAR Consolidation On An ECU
By Mentor, a Siemens Business - 08 Jan, 2020 - Comments: 0

Current approaches used to tackle the complexities described earlier in this paper (cockpit domain units) are both cost-prohibitive and lacking in performance. Utilizing virtualization in automotive software architecture provides a better approach when taking on these complexities. This can be achieved by encapsulating different heterogeneous automotive platforms inside virtual machines running... » read more

Configurable, Easy-To-Use, Packaged Reliability Checks
By Mentor, a Siemens Business - 18 Dec, 2019 - Comments: 0

Using a packaged checks flow lets designers quickly select, configure and run custom reliability checks and check combinations to help design companies achieve today’s demanding time-to-market schedules while ensuring product reliability. To read more, click here. » read more

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