Author's Latest Posts


Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes


Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

FinFET Impacts For Reducing Physical IP Power Consumption


FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and processā€induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more