7nm Power Issues And Solutions

By Preeti Gupta - 16 Nov, 2016 - Comments: 0

Being able to achieve 35% speed improvement, 65% power reduction and 3.3X higher density makes adopting a 7nm process for your next system-on-chip (SoC) design seem like an easy decision. However, with $271 million in estimated total design cost and 500 man-years it would take to bring a mid-range 7nm SoC to production, companies need to carefully weigh the benefits against the cost of designin... » read more

Can RTL Clock Power Be Accurate Enough For Sub-20nm Multi-GHz Designs?

By Preeti Gupta - 11 Sep, 2014 - Comments: 0

The Register Transfer Language (RTL) has increasingly been adopted to enable early and high-impact power decisions. As a cycle-accurate hardware abstraction, RTL is expected to deliver reasonable power accuracy. Clocks are particularly important to analyze and optimize for power. They switch the most and drive the highest loads. Clock gating is an effective power reduction technique that shuts ... » read more

RTL Design-for-Power In Mobile SoCs

By Preeti Gupta - 11 Jul, 2013 - Comments: 0

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz. Mobile system-on-chips (SoCs) continue to clock faster and pack more functionality, yet are required to consume lower power for battery life and thermal considerations. Power consumption is a k... » read more

Better Power Planning

By Preeti Gupta - 12 Jan, 2012 - Comments: 0

By Preeti Gupta Making the right architectural decisions for controlling power consumption and ensuring power integrity requires early identification and quantification of varying current demands in a semiconductor design. Furthermore, low-power designs pose complexities for power verification, such as significant current surges caused by clock gating or power gating transitions. In last mo... » read more

Power Delivery Networks

By Preeti Gupta - 01 Dec, 2011 - Comments: 0

By Preeti Gupta That power is now at the forefront of semiconductor design is no secret. It is also true that lowering power consumption drives product competitiveness and green technology—even more so in today’s mobile-driven market. But the same drive for lower power also increases the complexity of ensuring the power integrity of a system-on-chip (SoC). The power delivery network (PD... » read more