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IBM Unloads Chip Biz To GF
By The SE Staff - 20 Oct, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus After months of on-again, off-again negotiations, [getentity id="22306" comment="IBM"] agreed to hand over its Microelectronics unit to [getentity id="22819" comment="GlobalFoundries"] for $1.5 billion—meaning IBM will actually pay GlobalFoundries that amount to get rid of what has become an albatross for Big Blue. To really sweeten the deal, GlobalFoundr... » read more

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

What Happened To 450mm?
By The SE Staff - 17 Jul, 2014 - Comments: 1

By Mark LaPedus, Ed Sperling & Katherine Derbyshire There was a time not very long ago—one process node, in fact—when the economic momentum of Moore’s Law seemed unstoppable with a combination of extreme ultraviolet lithography, larger wafer sizes and a variety of new materials. Shrinking feature sizes is still technically possible, but certainly not with the same promised economic benef... » read more

Mentor Buys Berkeley Design
By The SE Staff - 21 Mar, 2014 - Comments: 0

Mentor Graphics announced today that it has acquired Berkeley Design Automation, staking a claim on the expanding market for analog, mixed-signal and RF verification. The deal puts Mentor on firm footing against Synopsys and Cadence, just as the opportunity for the Internet of Things (IoT), including automotive and medical design, begins to show real promise. Until this move, Mentor has larg... » read more

Cadence To Buy Forte
By The SE Staff - 05 Feb, 2014 - Comments: 2

Cadence agreed to buy Forte Design Systems for an undisclosed sum, enhancing its footprint in the high-level synthesis market as higher levels of abstraction gain traction across the SoC world. For the better part of a decade high-level synthesis (HLS) has been a market opportunity that was just around the next bend, along with electronic system-level design and SystemC modeling. Mentor Grap... » read more

Defining The Next Standard Cell
By The SE Staff - 22 Jan, 2014 - Comments: 1

Synopsys, Intel and IBM all contributed technology to Si2 to create a standard version of parameterized cells, or PCells, for mixed-signal designs. The move is an attempt to smooth out design incompatibilities using Synopsys and Cadence technology. Cadence is the clear market leader in this space. But as more technology is developed using different vendors'  tools for integration in complex... » read more

Calendar Of Events
By The SE Staff - 01 Nov, 2013 - Comments: 0

Industry Events   December 2014 January February March March 24-28, DATE, Dresden, Germany   Vendor-Sponsored Events November   2014 January February March April May May 23, Second Workshop on Virtual Prototyping and Embedded Systems ViPES, Phoenix, Ariz. » read more

Experience Required
By The SE Staff - 30 May, 2013 - Comments: 0

Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the evolution of commoditization (chip hardware) and customization (software). But many design engineers remain cautious about the actual application of experiences to their work. What is driving this emphasis on expe... » read more

Beyond Software: The Virtual-Machine Supply System
By The SE Staff - 25 Apr, 2013 - Comments: 0

It’s no secret that EDA and IP companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Around 2000, the industry was very fragmented. Mobile-chip and IP vendors worked with handset makers, who then partnered with operating-system (OS) suppliers and finally network operators. The next 12 years resulted in various combinati... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

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