Author's Latest Posts


How Low Can You Go? Pushing The Limits Of Transistors


Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe®) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL™) and Universal Chiplet Interconnec... » read more

How To Build A Rock-Solid Software Security Initiative


Application security testing is the starting block, not the finish line. While a critical component of every security program, the “penetrate and patch” approach is not a strategy. You need a complete program to lower risk exposure, measure progress, and demonstrate results. The most effective AppSec programs—or software security initiatives—are fine-tuned to their respective organiz... » read more

Best Practices For Cybersecurity-Aware SoC Development With ISO 21434


The growth of electronics in cars is exposing a new vector for cyberattacks on owners and automotive companies’ reputations. The potential human cost of an attack on the car’s electronics is driving urgency in the adoption of cybersecurity-aware practices, from OEMs and Tier 1s to every component supplier in the automotive industry. The standard “ISO/SAE 21434:2021 Road vehicles — Cyber... » read more

Using Machine Learning To Automate Debug Of Simulation Regression Results


Regression failure debug is usually a manual process wherein verification engineers debug hundreds, if not thousands of failing tests. Machine learning (ML) technologies have enabled an automated debug process that not only accelerates debug but also eliminates errors introduced by manual efforts. This white paper discusses how verification engineers can more efficiently analyze, bin, triage... » read more

Achieve 10X Faster CDC Debug Leveraging Machine Learning


Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations ... » read more

What Designers Need To Know About USB Low-Power States


In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond t... » read more

Reducing Simulation Regression Turnaround Time With Dynamic Performance Optimization


No single step in the development of semiconductor devices is more sensitive to speed than functional simulation. A modern system-on-chip (SoC) design simulates billions of cycles of operation in the process of completing the verification plan and achieving coverage goals. To validate full system functionality, many of these simulations include running code on one or more embedded processors. E... » read more

Securing Next-Gen 5G And IoT With Defensics Fuzzing


Expansion of the IoT brings new security challenges The evolution of 5G technologies continues to drive advancement in Internet of Things (IoT) devices and their applications. By 2025, experts predict there will be nearly 4 billion IoT mobile connections in the world, and more than 64 billion IoT devices by 2026. In addition to enabling superior performance and efficiency, 5G expands the ... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes


This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

← Older posts Newer posts →