Author's Latest Posts


A Survey Of Recent Advances And Research Activities In Wireless NoC Security


A technical paper titled “Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures” was published by researchers at Macquarie University (Sydney). Abstract: "Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures. Its adoption has become widespread due to t... » read more

Improving The Retention Characteristics Of 3D NAND Flash Memories


A technical paper titled “3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer” was published by researchers at Myongji University, Soongsil University, and Seoul National University. Abstract: "To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeat... » read more

A New Architecture And Verification Approach For Hardware Security Modules


A technical paper titled “The K2 Architecture for Trustworthy Hardware Security Modules” was published by researchers at MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) and New York University. Abstract: "K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation ... » read more

Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices


A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

A Modelling Approach To Well-Known And Exotic 2D Materials For Next-Gen FETs


A technical paper titled “Field-Effect Transistors based on 2-D Materials: a Modeling Perspective” was published by researchers at ETH Zurich. Abstract: "Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity... » read more

Benefits Of Using Wireless Communication Technologies In Power Electronics Systems Employing AGDs


A technical paper titled “Wireless Control of Active Gate Drivers for Silicon Carbide power MOSFETs” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract: "Active Gate Drivers (AGDs) enhance controllability and monitoring of switching devices, especially for fast switching Silicon Carbide (SiC) power Metal-Oxide-Semiconductor Field-Effect Transis... » read more

CPU Fuzzing Via Intricate Program Generation (ETH Zurich)


A technical paper titled “Cascade: CPU Fuzzing via Intricate Program Generation” was published by researchers at ETH Zurich. Abstract: "Generating interesting test cases for CPU fuzzing is akin to generating programs that exercise unusual states inside the CPU. The performance of CPU fuzzing is heavily influenced by the quality of these programs and by the overhead of bug detection. Our a... » read more

Light-Matter Interaction In Van Der Waals Nanophotonic Devices


A technical paper titled “Deeply subwavelength integrated excitonic van der Waals nanophotonics” was published by researchers at University of California Los Angeles, University of Washington Seattle, and Auburn University. Abstract: "The wave nature of light sets a fundamental diffraction limit that challenges confinement and control of light in nanoscale structures with dimensions signi... » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)


A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Analyzing The U.S. Advanced Packaging Ecosystem With Countermeasures To Mitigate HW Security Issues


A technical paper titled “US Microelectronics Packaging Ecosystem: Challenges and Opportunities” was published by researchers at University of Florida, University of Miami, and Skywater Technology Foundry. Abstract: "The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technologica... » read more

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