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RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

Transferring Qubits Directly Between Quantum Computing Microchips (U. of Sussex/ Universal Quantum)
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "A high-fidelity quantum matter-link between ion-trap microchip modules" was published by researchers at University of Sussex, Universal Quantum Ltd, University College London and University of Bristol. “As quantum computers grow, we will eventually be constrained by the size of the microchip, which limits the number of quantum bits such a chip can accommodate.... » read more

Wafer Scale Transfer of 2D Materials, Graphene
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A new technical paper titled "Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements" was published by researchers at Infineon Technologies AG, RWTH Aachen University, Protemics, and Advantest. Abstract "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requ... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Mitigating Silent Data Corruptions in High Performance Computing
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A new technical paper titled "Mitigating silent data corruptions in HPC applications across multiple program inputs" was published by researchers at University of Iowa, Baidu Security, and Argonne National Lab. The paper was a Best Paper finalist at SC22. The researchers "propose MinpSID, an automated SID framework that automatically identifies and re-prioritizes incubative instructions in a... » read more

Automotive E/E Architectures with Safety Related Availability (SaRa) Requirements For Highly Autonomous Driving
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Multi-objective optimization for safety-related available E/E architectures scoping highly automated driving vehicles" was written by researchers at Robert Bosch GmBbH and University of Luxembourg. Abstract: "Megatrends such as Highly Automated Driving (HAD) (SAE ≥ Level-3), electrification, and connectivity are reshaping the automotive industry. Together with th... » read more

3-Terminal Thermal Transistor With Thermal Measurements For The Switching And Amplification
By Technical Paper Link - 29 Jan, 2023 - Comments: 1

A technical paper titled "A three-terminal magnetic thermal transistor" was published my researchers at Rice University (Texas). Abstract "Three-terminal thermal analogies to electrical transistors have been proposed for use in thermal amplification, thermal switching, or thermal logic, but have not yet been demonstrated experimentally. Here, we design and fabricate a three-terminal magneti... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

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