Author's Latest Posts


Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application


This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination... » read more

A Guide To Fast Optimal Solutions To Complex Problems For Quantum Computers


Most people have already heard the term “quantum computer.” There has been a lot of interest in quantum computers over the last few years, with great expectations that they will dramatically change the world soon. These days, we use computers all the time in our daily lives. Personal computers and smartphones are obvious computers, but there are many more computers hidden in plain sight aro... » read more

Semiconductor Manufacturing Equipment And Measures To Protect The Earth’s Environment


Over the years, many countries on our planet have made significant efforts to develop their economies, achieving remarkable advancements in a wide variety of industries. However, the progress came with a great cost to the Earth’s environment. The destruction of nature has occurred frequently as a matter of course, to such an extent that in some regions it would hardly be possible to restore n... » read more

Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning


We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Yield Enhancement Technology: Efforts To Suppress Nanosized Particles In Semiconductor Production Equipment


The currently dominant semiconductor process size is in the range between a few and a few dozen nanometers. That means if a nanosized particle smaller than a virus (hereinafter simply “particle”) is present on a silicon substrate, it could cause a defect in the semiconductor device, lowering the production yield (i.e., the percentage of good chips produced in a manufacturing process). Preve... » read more

Consideration Of Missing Defect Suppression Technique In EUV Hole Patterning


This study focused on the defect behavior analysis with CD variation on EUV via hole pattern using photolithographic process and etch transfer performance. While defect requirements are not as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult... » read more

Efforts to Suppress Nanosized Particles in Semiconductor Production Equipment


The currently dominant semiconductor process size is in the range between a few and a few dozen nanometers. That means if a nanosized-particle smaller than a virus (hereinafter simply “particle”) is present on a silicon substrate, it could cause a defect in the semiconductor device, lowering the production yield (i.e., the percentage of good chips produced in a manufacturing process).... » read more