Author's Latest Posts

System Level Test — A Primer: White Paper

By Teradyne - 10 Jan, 2023 - Comments: 0

As semiconductor geometries become smaller and greater complexity is pushed into chips or packages, System Level Test (SLT) is becoming essential. Peter Reichert, System Architect for Teradyne’s System Level Test division discusses what System Level Test is, and how it can improve final product quality and reduce time to market. Click here to download the white paper. » read more

System Level Test — A Primer

By Teradyne - 07 Jun, 2022 - Comments: 0

As semiconductor geometries become smaller and greater complexity is pushed into chips or packages, System Level Test (SLT) is becoming essential. SLT is testing a device under test (DUT) as it is used in the end-use system, by merely using it rather than creating test vectors, as is done with traditional automated test equipment (ATE). Tests are still written but in a different way… Pete... » read more

Programming Devices At In-Circuit Test

By Teradyne - 06 Dec, 2014 - Comments: 0

Manufacturers have a great deal of flexibility when deciding where and how to program their devices. Components can be programmed at many stages during the procurement and manufacturing process. This Teradyne white paper explains why in-circuit test is the ideal stage in the production line to program firmware into components or data into flash memory. Download this white paper to learn h... » read more