Author's Latest Posts

Open IP Development Tools
By Various Writers - 29 Nov, 2012 - Comments: 0

By Pascal Chauvet How much time have you wasted trying to understand software tools by deciphering the logic of their creator? I always find it very frustrating to be limited by features and tool capabilities that do not do exactly what I want, or which do not work at all with my other applications. We are engineers! We can learn and adapt, but we often want to be able to extend and improve th... » read more

Taming The Challenges Of 20nm Custom/Analog Design
By Various Writers - 29 Nov, 2012 - Comments: 0

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers. To view this white paper, click here. » read more

Questa Covercheck: An Automated Code Coverage Closure Solution
By Various Writers - 29 Nov, 2012 - Comments: 0

This white paper explores the debugging aspect of code coverage closure, and how Questa CoverCheck’s unique ability of formal technology can automatically generate simulation exclusion files to improve code coverage results while reducing the amount of time wasted trying to hit unreachable states. To download this white paper, click here. » read more

Considerations for Porting a Bulk CMOS Design to FD-SOI
By Various Writers - 16 Nov, 2012 - Comments: 0

Technologists describe a straight port of an existing bulk CMOS design to FD-SOI at the same node, obtaining the value of fully depleted SOI for a modest redesign effort. Considerations Bulk to FD - Release » read more

Reducing IC Cycle Time With Calibre
By Various Writers - 15 Nov, 2012 - Comments: 0

Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physica... » read more

Automated Assembly And IP Integration Techniques For SoCs
By Various Writers - 08 Nov, 2012 - Comments: 0

Over the past few years, the consumer revolution has generated a significant growth of system-on-a-chip (SoC) designs mainly in the area of consumer electronics. The consumer revolution has led to a trend in convergence of applications on a single device. The biggest such example is the Smartphone or Tablet – handheld devices such as the iPhone or the iPad. These devices can enable consumers ... » read more

Technologies For Power, Signal, Thermal And EMI Sign-off
By Various Writers - 08 Nov, 2012 - Comments: 0

This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines. To download this white paper, click here. » read more

Challenges For Patterning Process Models Applied To Large Scale
By Various Writers - 25 Oct, 2012 - Comments: 0

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist... » read more

Optimizing And Maintaining A High-Performing Design Environment
By Various Writers - 25 Oct, 2012 - Comments: 0

To maximize your investment in electronic design automation (EDA) tools, your infrastructure and processes must be optimized for growing and frequently changing design needs. Cadence Client Technology Solutions is dedicated to enhancing EDA tool performance, ensuring stability, and removing critical bottlenecks. Through close collaboration with hundreds of customers worldwide, we have unique in... » read more

Design Solutions For 20nm And Beyond
By Various Writers - 25 Oct, 2012 - Comments: 0

The consumer’s insatiable demand for greater performance, a shrinking form factor and extended battery life, all while continuing the trend for lower end user cost is the driving force behind the semiconductor industry’s rapid evolution to ever smaller process geometries. As with many of the previous process geometry shrinks, there will be the usual concerns about the increase in design ... » read more

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