Author's Latest Posts

How To Achieve 10X Faster Power Integrity Analysis And Signoff
By Various Writers - 04 Dec, 2013 - Comments: 0

In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other te... » read more

SpyGlass Flow For Xilinx FPGA
By Various Writers - 04 Dec, 2013 - Comments: 0

As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 04 Dec, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

A Guide To Power-Aware Memory Repair
By Various Writers - 04 Dec, 2013 - Comments: 0

The number of embedded memories contained within an SoC continues to grow rapidly. This growth has driven the need for rethinking manufacturing test strategies as embedded memories represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must incorporate some form of repair methodology in o... » read more

IEEE 1801 UPF Tutorial
By Various Writers - 22 Nov, 2013 - Comments: 0

This tutorial from DVCon 2013 covers the basics of Accellera UPF and then focuses on the features of IEEE 1801 that enable the description of more sophisticated power management systems. The tutorial also provides recommendations regarding migration from Accellera UPF to IEEE 1801 and the methodology changes that are required. And, it presents a UPF-based design flow highlighting the practical ... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 21 Nov, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

HDMI 2.0 Design And Verification Challenges
By Various Writers - 21 Nov, 2013 - Comments: 0

HDMI designs face challenges with respect to run time and memory consumption due to the huge size of HDMI frames. Scrambling adds more complexity and designs face synchronization and timing challenges. Similar challenges are faced during the functional verification of systems-on- chip (SoCs) including HDMI interfaces. These challenges can be addressed using HDMI verification IP (VIP). To dow... » read more

Verifying Cache Coherency Protocols With Verification IP
By Various Writers - 21 Nov, 2013 - Comments: 0

The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
By Various Writers - 07 Nov, 2013 - Comments: 0

Synopsys is a leading EDA company with an extensive portfolio of licensable DesignWare intellectual property (IP). The portfolio includes interface IP, analog IP, embedded memories, and logic libraries. Although most chip designers know that DesignWare IP also includes licensable CPU cores and subsystems, many are surprised to learn that Synopsys is second only to ARM in the number of chips tha... » read more

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