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PCIe In High-Performance FPGAs


In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, what are the factors that can assure such performance and speed? The value and success of today’s high performance computing applications in the areas of DNA Sequencing, High Frequency Trading (HFT) and Encryption/Decryption are predicated upon how fast data can be t... » read more

Inside UVM, Take Three


The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Inside UVM, Take Two


In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

Inside UVM


We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount of the verification effort needed for this type of SoC - the required manpower and time to get the job done is absolutely mind-boggling. Thankfully, we have several pre... » read more