Newsletters Archive - Page 37 of 66 - Semiconductor Engineering

IoT, Security & Automotive – 06/06/2019
By Jesse Allen - 06 Jun, 2019 - Comments: 0

Top Stories Machine Learning Drives High-Level Synthesis Boom As endpoint architectures get more complicated, EDA tool becomes key tool for experimenting with different options. Accelerating Endpoint Inferencing Machine learning, with the correct hardware infrastructure, may soon reach endpoints. Speeding Up AI Achronix's CEO explains where the main bottlenecks are and how to solve th... » read more

System-Level Design – 05/30/2019
By Jesse Allen - 30 May, 2019 - Comments: 0

Top Stories How To Integrate An Embedded FPGA Adding an eFPGA into an SoC is more complex than just adding an accelerator. Why IP Quality Is So Difficult To Determine How it is characterized, verified and used can have a big impact on reliability and compatibility in a design. Adding Order And Structure To Verification How industry experts reacted to their first encounter with a forma... » read more

Manufacturing, Packaging & Materials – 05/23/2019
By Jesse Allen - 23 May, 2019 - Comments: 0

Special Report 3D NAND Race Faces Huge Tech And Cost Challenges Shakeout looms as vendors struggle to find ways to add more layers and increase density. Top Stories SiC Demand Growing Faster Than Supply High-voltage applications such as electric vehicles raise specter of shortage and higher prices. Partitioning In 3D Interconnects, bonding and the flow of data in advanced packaging. B... » read more

Low Power High Performance – 05/09/2019
By Jesse Allen - 09 May, 2019 - Comments: 0

Top Stories The Growing Uncertainty Of Sign-Off At 7/5nm Checking the electrical characteristics of circuits is becoming much more challenging. The Limits Of Energy Harvesting Why the promise of unlimited power in end devices has achieved only spotty success. Raising The Abstraction Level For Power Finding the right abstraction for power analysis and optimization comes from tool integ... » read more

Test, Measurement & Analytics – 05/07/2019
By Jesse Allen - 07 May, 2019 - Comments: 0

Special Report 5G Heats Up Base Stations Inefficient conversion of RF to digital and continuous connectivity issues are causing thermal problems, threatening signal integrity and reliability. Top Stories Challenges In Making And Testing STT-MRAM Next-gen memory offers speed of SRAM and unlimited endurance, but it's not a simple technology to work with. Gaps Emerge In Automotive Test Re... » read more

IoT, Security & Automotive – 05/02/2019
By Jesse Allen - 02 May, 2019 - Comments: 0

Top Stories Make Your Own Energy Efficient use of power and energy in electric vehicles and smart buildings will require innovative thinking. Creating A Roadmap For Hardware Security Government and private organizations developing blueprints for semiconductor industry as threat level rises. April Startup Funding: Corporate Gushers Money pours into startups with more big investments on... » read more

System Level Design – 04/25/2019
By Jesse Allen - 25 Apr, 2019 - Comments: 0

Special Report The Case For Embedded FPGAs Strengthens And Widens Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream. Top Stories Automotive, AI Drive Big Changes In Test DFT strategies are becoming intertwined with design strategies at the beginning of the design process. When Verification Leads Expe... » read more

Manufacturing, Packaging & Materials – 04/18/2019
By Jesse Allen - 18 Apr, 2019 - Comments: 0

Top Stories Lithography Options For Next-Gen Devices EUV is the clear winner down to 5nm, but what comes after that may be a combination of tools and techniques. Inspecting IC Packages Using Die Sorters Die sorters are crucial for finding cracking defects in optoelectronics, sensors and advanced nodes. Moore's Law Now Requires Advanced Packaging Experts at the Table, part 1: Shrinking... » read more

Low Power High Performance – 04/11/2019
By Jesse Allen - 11 Apr, 2019 - Comments: 0

Top Stories Target: 50% Reduction In Memory Power Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level. Low Power Meets Variability At 7/5nm Reductions in voltage, margin and increases in physical effects are making timing closure and signoff much more difficult. Optimization Challenges For Safety And Securi... » read more

Test, Measurement & Analytics – 04/09/2019
By Jesse Allen - 09 Apr, 2019 - Comments: 0

Top Stories Racing To The Edge The opportunity is daunting, but so are the challenges for making all the pieces work together. New Approaches To Security Data analytics, traffic patterns and restrictive policies emerge as ways to ensure that systems are secure. 3D NAND Metrology Challenges Growing Rising costs and gaps in equipment emerge as technology scales; new tools under developm... » read more

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