January 2012 - Page 3 of 4 - Semiconductor Engineering


32nm SOI is GloFo Fab 8′s 1st Silicon


Excellent news for the fast-growing SOI community:  the first chips produced at GlobalFoundries’ “Fab 8″ in upstate New York are based on IBM’s latest, 32nm SOI chip technology. In a joint press release, the two companies announced that the chips will be used by customers in networking, gaming and graphics. While the new chips began initial production at IBM’s 300mm fab in East... » read more

Substrates for Semiconductor Packaging


2012 Market Outlook for Laminate and Leadframe Materials By Jan Vardaman, TechSearch International, and Dan Tracy, SEMI Combined, laminate substrates and leadframes will represent an estimated US$ 13.3 billion market in 2011 and is forecasted to reach $14 billion in 2012. This is larger than the revenues for silicon wafers (including silicon-on-insulator wafers) of $10.3 billion in 2011 and... » read more

When Worlds Collide: Saving Power In Communications Applications


By Ann Steffora Mutschler The interplay of hardware and software is a given in every device that contains a semiconductor chip, but is typically felt more acutely in communications applications given the extremely close dependencies for everything power-related. Managing power in these situations just gets more challenging as consumers demand more and better applications on their tablets, smar... » read more

What Happens When The Plug Is Pulled


By Pallab Chatterjee The Consumer Electronics Show featured a large variety of new devices and peripherals for the mobile and portable space. In addition to the tablet, which is the fastest growing data-consumption platform, and the laptop, which is the fastest-growing data creation and modification platform, there are a large number of peripheral devices that are being released. These devi... » read more

The Next Big Challenge


By Ed Sperling Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be. There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across... » read more

Status Report: Power-Aware Design Flow


By Ann Steffora Mutschler While the term “design flow” can be a moving target, there are some specific requirements for a low-power/power-aware tool flow. Looking at this from a high level, where is the industry today, and where is it headed? There are really two sides to power, which are almost like two sides of the same coin: power consumption and power integrity. And both of those ar... » read more

Rethinking Good Enough


By Ed Sperling Power has been elevated from an afterthought to one of the top considerations and tradeoffs in SoC design, edging out performance and area in many cases and in some cases even cost and features. Tradeoffs in design always change, depending upon what the most pressing concern is among consumers at any time. For decades, performance was always the top of anyone’s list, follow... » read more

How Long Will 28nm Last?


By Ann Steffora Mutschler As soon as a next generation semiconductor manufacturing process node is out, bets are taken on just how long the current advanced process node will last. The 28/20nm transition is no exception. There is certainly a benefit to moving from 40nm to 28nm. The  availability of high-k/metal gate technology offers quite a few advantages in terms of power reduction... » read more

Thinking Differently About Power


By Ed Sperling Battery life and lower electricity bills are now marketing tools for makers of SoCs, the mobile devices they go into, and servers that power data centers. A smart phone battery that lasts through the day without a charge, even when the user is playing high-action games, is a lot more attractive than one lasting only a few hours. And a data center electricity bill that shows a sh... » read more

Fill Challenge Solved: Why SmartFill is as Good as it Sounds


by Jean-Marie Brunet Among the many steps involved with chip design, there is one known by the deceptively simple name of “fill.” Fill involves adding shapes or polygons to the design that are structural, not logical. That is, they ensure manufacturability by making sure each layer (metal, poly, diffusion) has a proscribed density. As easy as this sounds, fill can be tricky, and the fill... » read more

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