Jean-Marie Brunet

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Jean-Marie Brunet is the Senior Marketing Director for the Emulation Division at Mentor, a Siemens Business. He has served for over 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among others. Brunet holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France.

Author's Latest Posts

5G Brings New Verification Challenges
By Jean-Marie Brunet - 23 Apr, 2020 - Comments: 0

In the summer of 2018, Siemens raised a few eyebrows within the verification community when we acquired Sarokal, based in Finland. What that community did not piece together at the time was that Sarokal is the leader in 5G testing and has a seasoned team of people that have work closely with leading telecommunication companies to provide hardware and software solutions for fronthaul system test... » read more

5G Needs Cohesive Pre- And Post-Silicon Verification
By Jean-Marie Brunet - 24 Oct, 2019 - Comments: 1

While 5G doesn’t start from a clean slate, it does make significant changes to the 4G architecture. These changes mean that the ecosystem from chips to operators is evolving, giving opportunities to more companies to engage in this growing market. Realignment in fronthaul, midhaul and backhaul In particular, the radio access network (RAN) has been redefined as Cloud RAN (sometimes called ... » read more

Verifying AI Designs Thoroughly And Quickly
By Jean-Marie Brunet - 31 Jan, 2019 - Comments: 0

You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

The Route To Faster Physical Verification And Better Designs
By Jean-Marie Brunet - 18 Sep, 2014 - Comments: 0

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

It’s Time to Bring GDS “Reality” Into Routing Closure
By Jean-Marie Brunet - 17 Jul, 2014 - Comments: 0

By Nancy Nguyen and Jean-Marie Brunet Imported cells, whether macros, standard cells, or intellectual property (IP), are a common element of today’s integrated circuit (IC) designs. Historically, when designers incorporate these cells into a design, they import them using an abstract format defined by a layout exchange format (LEF) file. This abstract view provides basic information about th... » read more

Routing Closure Challenges At 28nm And Below
By Jean-Marie Brunet - 03 Jan, 2014 - Comments: 1

As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more

Reducing The Tapeout Crunch With Signoff Confidence
By Jean-Marie Brunet - 17 Oct, 2013 - Comments: 1

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays. At leading-edge nodes, however, we’re running into some new problems that need new solutions. We all know design rule numbers and complexity are going through the roof as we try to use 1... » read more

I Just Want Closure!
By Jean-Marie Brunet - 15 Aug, 2013 - Comments: 0

By Jean-Marie Brunet We all know it by now, but let’s say it one more time for the cameras—the level of complexity of closure at 20 nm and below is considerably higher than for any previous nodes. While the migration of manufacturing requirements into design started with a few suggested activities at 65 nm, such as recommended rules compliance, lithography checks, and critical area analysi... » read more

Let’s All Meet At The Via Bar!
By Jean-Marie Brunet - 30 Jun, 2013 - Comments: 0

By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

Challenges Of Physical Design Closure
By Jean-Marie Brunet - 22 Oct, 2012 - Comments: 0

By Jean-Marie Brunet A clear trend in IC design is that with each smaller process node, reaching design closure gets more difficult, expensive, and time consuming. Printing ever-smaller features with 193nm wavelength light has introduced unprecedented levels of manufacturing challenges, which are addressed with a growing set of complex design rules (DRC) and design for manufacturing (DFM) cons... » read more

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