Routing Closure Challenges At 28nm And Below

DRC and DFM clean still means there are hundreds to thousands of violations that need to be debugged and corrected.


As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, in fact, likely contain hundreds to thousands of violations that must be debugged and corrected. Today’s fast-paced market simply doesn’t provide the kind of leeway in tapeout schedules needed to accommodate such time-consuming corrections.

In this article, I’d like to take a closer look at two specific domains that are being affected by this mismatch: logical signal nets and pre-routing nets. At advanced nodes, we are seeing much greater visibility of signal nets issues, and even more so with pre-route problems.

Logical signal net routing is usually performed with the detail router, and it is usually the last thing design teams tackle. Historically, the detail router has done a good job of getting to manufacturing closure, and if you are working at mature process nodes, you probably don’t see many issues with signal nets.

However, at 28 nm and below, we have many more layers and gates than ever before, and more nets per typical block. Signal nets are presenting many issues with via topology, via type, and via enclosure. The challenge is to completely understand the complex design rules of these nodes, and ensure they are applied properly.

If you are designing at the bleeding-edge, you will have a large gap in technology between your router tech file and signoff rule deck. As a result, issues with signal nets are going to be very common, particularly because signal nets are very technology-dependent. The impact of the tech file/design rule gap will be seen most often around the routing of vias, and will be significantly affected by the amount of congestion in a design. As you implement your designs, it will be important to have an environment that understands the issues well, and can access the signoff checks as needed to ensure the routed design will be DRC/DFM-clean.

Pre-routing, on the other hand, is more independent of process nodes, but significantly affected by methodology. Pre-routing is a part of P&R, but it addresses very specific layout requirements, such as power and ground routing, and clock tree routing. It is usually performed before timing closure, during early floorplanning and macro block placement. Normally, designers complete the power and ground routing first, followed by the clock tree routing.

What makes pre-routing unique is that it is usually performed using a semi-automated technique, with some customization and programmable actions. Most commonly, design teams use the Tcl function of P&R to drive these semi-customized routings. However, when they run verification, they will routinely find many “small” issues, such as via misplacements, via arrays that don’t have the right enclosures, or tapping of power and ground that is not complete (Figure 1). Although these issues may seem quite small, and relatively easy to correct, they are very common, and they occur everywhere in the layout. With current pre-router methodology, there is no way to automatically fix them.

Figure 1. Via enclosure error (source: Mentor Graphics)

Additionally, when design teams begin including finFET transistors, there is a lot of concern with electromigration (EM) issues. Power to ground network routing becomes extremely important.

What we need is a technology that specifically understands this type of topology, and can apply signoff quality fixes automatically during the pre-route process. With capabilities that ensure the clean routing of the power ground network, address the issue of EM efficiently and accurately, and provide an automatic fixing solution that doesn’t rely solely on the tech file, but can refer to signoff checks when needed, such a technology would be an extremely important part of the P&R process at 28 nm and below.

Both signal net routing and pre-routing issues, if not addressed, have the same impact—they delay tapeout. At 28 nm and below, time to market gets shorter every day. Any technology that can help ensure DRC/DFM-clean routing results will help design teams use their precious time in the most efficient and profitable way possible


[…] seeing greater visibility of signal net issues and pre-route problems. To understand why, check out this article by Jean-Marie Brunet on Semiconductor […]

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