Transforming DRC Closure At Advanced Nodes


If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Veloce Coverage App And Veloce Assertion App Deliver Unified Coverage Methodology


The interoperability of the Veloce Coverage app and the Veloce Assertion app with other verification engines (simulation and formal) enables merging coverage collected by each engine and provides a cohesive coverage closure report and analysis flow. It enables the verification team and product-level management to make important decisions such as coverage closure sign-off, test quality analysis ... » read more

Unveil The Mystery Of Code Coverage In Low-Power Designs: Achieving Power Aware Verification


This paper discusses challenges in code coverage of low-power designs and approaches to overcome those challenges. Also explained is how total coverage results can be visualized in order to achieve verification closure in significantly less time. To read more, click here. » read more

Routing Closure Challenges At 28nm And Below


As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more