Systems & Design

Veloce Coverage App And Veloce Assertion App Deliver Unified Coverage Methodology

Improving confidence at every step of the design flow.


The interoperability of the Veloce Coverage app and the Veloce Assertion app with other verification engines (simulation and formal) enables merging coverage collected by each engine and provides a cohesive coverage closure report and analysis flow. It enables the verification team and product-level management to make important decisions such as coverage closure sign-off, test quality analysis and traceability from the specification to the design features and verification collateral. A unified coverage methodology is now a key requirement in the industry, and Veloce is well positioned to deliver it.

Coverage and assertions in Veloce Emulation
The Veloce Coverage app and Veloce Assertion app play a central role in bringing coverage and the use of assertions up to the system-level verification that will be run on a Veloce emulator.

The Veloce Coverage app supports code coverage (statement, branch, toggle and FSM) as well as functional coverage constructs (covergroup, coverpoint, bins, cross, etc.). Toggle coverage is supported at the gate level netlist as well. It is relevant when qualifying the stimulus to a region of the design in context to its output from a synthesis tool.

On any given run, the app allows the verification engineer to select whether to test the entire system or focus on one or more IP blocks. Those blocks will likely have been at least partially tested already during simulation, so Veloce can identify that in the UCDB and instrument the coverage that hasn’t been covered yet.

The Veloce Coverage app provides the following options to define the coverage scope of the design by the user:

  • Pass a cover file with regions of the design to cover or not cover
  • Pass UCDBs from prior runs in simulation or emulation

The latter option (that includes assertions as well) can be particularly useful if prior coverage from simulation/emulation engines needs to be omitted from future compiles.

Assertions, meanwhile, can be included at the simulation level and then used as-is during emulation. All assertion types are supported by the Veloce Assertion app. For ease of debug, the required set of assertions can be compiled into the design and then selectively enabled or disabled at runtime. This saves the compile time that would be necessary if the design had to be recompiled each time the new assertions are incorporated.

For ease-of-use flexibility, TCL and C-API interfaces are available to control enabling coverage and assertions at runtime. All the coverage and assertion constructs are synthesized and mapped into the Veloce platform. This provides an environment for the tests to run at full emulation speeds without impacting performance.

Plays well with other apps in all modes
Emulation can be performed in different ways to address different challenges. Examples include simulation acceleration, virtual system-level emulation and in-circuit emulation (ICE).

The Veloce Coverage app and Veloce Assertion app can be used regardless of the emulation verification use modes in effect.

Using both the Veloce Coverage app and Veloce Deterministic app in an ICE environment allows coverage collection from complex real-world stimulus to exercise the design under test (DUT).

Both apps can also be used alongside other Veloce apps like the Veloce Power and Veloce Design-for-Test (DFT) applications. In addition, the Veloce Coverage and Veloce Deterministic apps work with Veloce VirtuaLAB components that generate system-level traffic for stimulating the design. Together, these elements can be used to assemble a comprehensive digital twin of the design being tested, allowing a verification team to run a rich set of tests to ensure that even tough corner cases are checked out.

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