Shift Verification Left: AI Tools For Faster, Smarter Chip Design


Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

Formal Verification Fundamentals Remain Non-Negotiable In The New Verification Revolution


The semiconductor industry stands at a critical juncture. First-time silicon success rates have reached all-time lows, while design complexity continues to grow exponentially. System-on-chip designs now integrate billions of transistors, multiple processor cores, complex memory hierarchies, and sophisticated interconnect fabrics. In this environment, the stakes for verification accuracy have ne... » read more

Easier Assertion Development And Debug With Simulation Replay


By Vin Liao and Robert Ruiz Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit... » read more

Simulation Replay Tackles Key Verification Challenges


Simulation lies at the heart of both verification and pre-silicon validation for every semiconductor development project. Finding functional or power problems in the bringup lab is much too late, leading to very expensive chip turns. Thorough simulation before tapeout, coupled with comprehensive coverage metrics, is the only way to avoid surprises in silicon. However, the enormous size and comp... » read more

Verification In Crisis


Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been improving overall, as has the complexity of designs. For ASICs, 74% of the designs surveyed in the recent Wilson Research Group/Siemens EDA report have one or more processor cores, 52% have two or mor... » read more

Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs


A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

Formal Verification’s Usefulness Widens


Formal verification is being deployed more often and in more places in chip designs as the number of possible interactions grows, and as those chips are used in more critical applications. In the past, much of formal verification was focused on whether a chip would function properly. But as designs become more complex and heterogeneous, and as use cases change, formal verification is being u... » read more

Formal Verification Best Practices: Investigating A Deadlock


To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond. This translates very nicely using a type of SystemVerilog Assertion called “liveness propertie... » read more

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?


Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero risk of unwanted surprises escaping undetected into your end-product. In order of high-to-low probability, consider: The presence of a weird-yet-entirely-possible corner-case bug Bugs “insid... » read more

Veloce Coverage App And Veloce Assertion App Deliver Unified Coverage Methodology


The interoperability of the Veloce Coverage app and the Veloce Assertion app with other verification engines (simulation and formal) enables merging coverage collected by each engine and provides a cohesive coverage closure report and analysis flow. It enables the verification team and product-level management to make important decisions such as coverage closure sign-off, test quality analysis ... » read more

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