Challenges Of Physical Design Closure

Traditional approaches to achieving design closure cannot meet the demands of the newest designs for time-to-market and manufacturability.

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By Jean-Marie Brunet
A clear trend in IC design is that with each smaller process node, reaching design closure gets more difficult, expensive, and time consuming. Printing ever-smaller features with 193nm wavelength light has introduced unprecedented levels of manufacturing challenges, which are addressed with a growing set of complex design rules (DRC) and design for manufacturing (DFM) constraints. Traditionally, DRC and DFM issues could be largely managed within the physical design stage. After tapeout, the design would go through physical verification with a tool like Calibre (See Figure 1). Any violations would be read back into a layout editor and fixed manually or with ECO routing without creating new violations.

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Figure 1. The iterations between error fixing and signoff analysis are very challenging at advanced nodes.

This traditional approach to achieving design closure simply cannot meet the demands of the newest designs in terms of time-to-market and manufacturability. Rather than one iteration between signoff analysis and fixing, designers now face multiple iterations that may never converge. One of the key sources of difficulty is that the router technology files during layout in advanced-node designs are less complete and less precise than the golden signoff deck. As a new process node matures, the foundry’s design rules files—the SVRF decks—are continuously being updated to address manufacturing issues as they are discovered. The router’s technology files lag behind the SVRF, and are even unable to capture the complexity of some rules.

Hence, you have a DRC-clean design coming out of place and route that, when run through signoff analysis, actually has many violations. As you fix those violations, though, you may create new ones that won’t be detected until the design is again analyzed with the SVRF deck. There is no way to bridge this gap—you simply have to iterate between fixing and signoff analysis until you are satisfied with that the design will manufacture as expected.

From my point of view, the solution to the design closure challenges must come from EDA technology that combines the separate analyze-then-fix steps into one analysis-driven fixing flow. Perhaps the most important aspect of a flow that will analyze and fix DRC/DFM violations correctly in one pass is the use of golden signoff SVRF deck for both analyzing and driving repairs. This is the only sure way to reduce the signoff iterations that cost time and money. How would a flow like this work? Designers would use any place and route environment they want, tape out as usual and perform signoff analysis. But then, rather than reading the DRC/DFM errors back into the design environment—where the same router that couldn’t find the problems in the first place is tasked with fixing them—you would use the SVRF analysis to drive the fixes, thus insuring physical closure in that single pass.

The primary benefit of a tighter integration between analysis and fixing is a vast reduction in turn-around time by eliminating the multiple iterations needed now to reach closure. The design would be guaranteed DRC clean and highly manufacturable by the golden signoff tool used by every foundry. It would have the added benefits of removing late-stage surprises that can sink a design schedule.