By Michael P.C. Watts Directed Self Assembly (DSA) was the breakout subject at this year’s SPIE Advanced Lithography Conference. This conference is the biggest annual get together for lithography nerds, and I use it to keep up with the latest academic and industrial trends. Anyone who is anyone seems to be evaluating DSA. On a personal note, as it turns out, I did my PhD in block copolymer... » read more

By Ed Sperling Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Ap... » read more

By Achim Nohl Transaction-level models are the main building blocks of virtual prototypes, which are used for early software development. In my last blog post, I briefly introduced the different kinds of software tasks and the implications for models. Today, I want to talk about the modeling requirements for early SoC bring up. As I mentioned, understanding the software requirements correct... » read more

By Ann Steffora Mutschler From a planning perspective, creating derivative chips seems a straightforward task, but the process is much more complex than simply replacing or adding a peripheral—it starts with identifying the right team of engineers to perform that process. “One of the needs in the market is somebody to have vertical expertise to do derivative design and yet be cost-effec... » read more

By Pallab Chatterjee Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain. This was quite evident at a recent DesignCon panel dicussion on ... » read more

By Ann Steffora Mutschler With the cost of designing and producing even moderately advanced SoCs skyrocketing, semiconductor companies and systems houses must find ways to defray the cost across a larger number of end uses than ever. As such many companies have adopted a platform-based derivative design approach, with that the platform serving as the first SoC design of a new family. That s... » read more

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

By Ed Sperling Ever since verification IP was introduced it was seen as something that should be given away with purchased IP. The result was limited investment by IP vendors, frustration on the part of IP customers, and a market opportunity that nearly fizzled before it even began. But as the amount of commercially developed IP content continues to grow in ICs, the potential interactions ... » read more

By Kurt Shuler It may seem strange to link two interchip interface standards to the future of3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design SoCs in the near future. C2C and LLI: The first standards created with the “combo chip” in mind As you may already know, the purposes of the chip-to-chip (C2... » read more

By Frank Ferro As I prepare to hit Barcelona for Mobile World Congress, I get the feeling that this will be a ‘do-over’ of last month’s CES, only without all the HD and 3D TVs. Although wireless infrastructure and applications are a big part of MWC, at the device level, tablets and smartphones will continue to dominate all the discussions. Déjà vu, anyone? Yet the reality is we are in ... » read more