May 2012 - Page 4 of 6 - Semiconductor Engineering

NoC Power Benefits
By Various Writers - 24 May, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units... » read more

Understanding Via Effects
By Various Writers - 24 May, 2012 - Comments: 0

As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before... » read more

Tech Talk: Coherency’s Next Frontiers
By Ed Sperling - 23 May, 2012 - Comments: 0

Laurent Moll, CTO of Arteris, talks about new types of coherency and why it will be such a big challenge. [youtube vid=lufY9yDLjwE] » read more

Tech Talk: Cloud-Scale SoCs
By Ed Sperling - 23 May, 2012 - Comments: 0

Sonics CTO Drew Wingard talks about what's changing in SoC design as performance ramps up on mobile devices and power is ratcheted down to save battery life. [youtube vid=cdzhFCsLyyI] » read more

Endless Abstractions?
By Frank Schirrmeister - 22 May, 2012 - Comments: 1

By Frank SchirrmeisterHaving started my own career doing full custom layout, then moving though gates and RTL to transactions and embedded software, I always was a little bit concerned whether the industry would eventually run out of abstraction levels for me to adopt further upwards. It looks like there is plenty of head room.Last week I was in Munich attending the CDNLive! EMEA event. I was h... » read more

Technology Crossover Ahead
By Ed Sperling - 18 May, 2012 - Comments: 0

The attention showered upon NVM Express these days by both Synopsys (verification IP) and Cadence (subsystem) is significant. It’s the first significant opening in the enterprise computing space to emerge in years, and this is a market in which efficiency and performance are both measured and fully recognized. While SoC developers in the mobile space continue to develop power-management ca... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 11 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

Old Problem, New Solutions
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events. “These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Ment... » read more

Traversing The Abstraction Landscape
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

New Power Standards Ahead
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry. To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with l... » read more

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