July 2012 - Page 4 of 5 - Semiconductor Engineering

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

A customizable imaging spectrometer – otherwise known as a “hyperspatial imager”
By Michael Watts - 16 Jul, 2012 - Comments: 0

By Michael P C Watts A camera that can detect any color even IR and UV would be very useful for any number of inspection or detection tasks….. a “hyperspatial imager”. The classic RGB color camera is limited by the RGB color filters which detect a limited range of visible wavelengths, known as the “color gamut” of the camera. At Photonics West 2012 in San Francisco, a team from Ime... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 13 Jul, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Bridging The Rift Between Software And Hardware
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling As more computing is done on mobile devices rather than desktops, the idea of what constitutes good application software is changing. This addresses the key reason why some of advanced power-saving features built into chips were not utilized by software in the past. Unless the operating systems were specifically written for mobile devices, such as Android and iOS, the real f... » read more

28, 20nm Nodes Demand Advanced Power Management
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

Four Factors Driving Processor Choices
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Choosing processors for an SoC, a system-in-package, or even a complete system is becoming much more difficult, and the challenge is growing as demands on performance, power, area and time to market continue to increase. There are many reasons why this is becoming more difficult—and some designs will require more tradeoffs than others, depending upon IP re-use or a particul... » read more

Testing the Waters
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler Large semiconductor companies are now testing the waters in 3D design to determine how to best leverage the technology for lower power, better performance and additional architectural flexibility. As such, much work is being done to determine how exactly to achieve an optimum 3D design outcome. 3D is almost by definition an architectural approach to power sav... » read more

Architectural Changes Will Drive Miraculous 3D Gains
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power High-Performance Engineering sat down with Robert Patti, chief technology officer at Tezzaron Semiconductor, to discuss future challenges with regard to 2.5D and 3D design, including making tradeoffs and technical issues specific to 3D design. Tezzaron currently is working on 3D designs. LPHP: What is the starting point technically to achieve the gre... » read more

Stacking The Deck
By Matt Elmore - 12 Jul, 2012 - Comments: 0

By Matt Elmore Can we finally say that 3D-IC design has emerged from the realm of theory and research to actual commercial implementation? Xilinx recently announced initial shipments of its Virtex-7 H580T FPGA, described as “The world’s first 3D heterogeneous all programmable product.” The benefits of 3D implementation are many, as are its challenges. One of the hottest 3D-IC topics t... » read more

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