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Signal Integrity’s Growing Complexity


By Matt Elmore In Part 1, we reviewed the importance of simultaneous switching output (SSO) timing and the challenges associated with double data rate (DDR) simulation complexity. DDR memory interfacing has reached incredible levels of performance (17 Gb/s), requiring precise quantification and reduction of noise. In order to account for each noise contributor, we must model systems end-to-... » read more

Signal Integrity’s Growing Complexity


By Matt Elmore While in the market for a memory upgrade recently, I was surprised by the availability of commercial DDR memories. You can get 8GB of DDR3 memory, transferring 17GB/s, relatively inexpensively. The progress in memory design is outstanding. From smartphones to gaming PCs, quick communication between the IC and off-chip memory is key to enabling the performance we demand in the... » read more

Stacking The Deck


By Matt Elmore Can we finally say that 3D-IC design has emerged from the realm of theory and research to actual commercial implementation? Xilinx recently announced initial shipments of its Virtex-7 H580T FPGA, described as “The world’s first 3D heterogeneous all programmable product.” The benefits of 3D implementation are many, as are its challenges. One of the hottest 3D-IC topics t... » read more

Top 5 Reasons For Power Delivery Failure


By Matt Elmore Technology scaling has brought with it a myriad of causes for power delivery network (PDN) failure. Even a few years ago, it was simply enough to run static and dynamic power analysis to expose any voltage drops caused by weak power routing. No one cared about modeling the package and PCB. To account for clock jitter, you could simply throw in a whole nanosecond of clock uncerta... » read more

Chip-Package-System Co-Design


By Matt Elmore This year’s DesignCon 2011 featured a multitude of advanced topics pertaining to IC design. One topic that came up repeatedly was chip-package-system (CPS) co-design. In each area of application, from mobile to automotive, IC designers have prioritized the need to analyze the chip, package, and PCB as complete system, rather than independent projects. The old days of margins, ... » read more

What is CPS?


CPS stands for Chip-Package-System. It represents a paradigm shift from the old partitioned approach of IC design into a cohesive methodology that considers the ecology of the system as comprised of the chip, package and board. Today’s design requirements are calling for a revisit to the way we look at IC design and validation. Companies no longer can afford to view design with a silo-base... » read more