Chip-Package-System Co-Design

Next-generation chip modeling will require a much better model of the noise source.


By Matt Elmore
This year’s DesignCon 2011 featured a multitude of advanced topics pertaining to IC design. One topic that came up repeatedly was chip-package-system (CPS) co-design. In each area of application, from mobile to automotive, IC designers have prioritized the need to analyze the chip, package, and PCB as complete system, rather than independent projects. The old days of margins, overdesign, and finger-crossing are no longer feasible. As technology scales, the increased electrical interaction between the chip, package, and PCB has caused CPS co-design to enter the foreground of every project manager’s mind. In order to facilitate CPS analysis, an accurate representation of the die is absolutely necessary to model the complexity of the noise source: the chip.

Chip power models include the die-level parasitics as well as the instance switching noise. In order to enable such varied applications such as EMI, SSO timing, and power noise analysis, the parasitic network of the power delivery route needs to be accurate over a broad frequency range. The parasitic network is distributed over the die, representing region-based impedance. Transistor switching noise is modeled by region-based current sources, which capture the transient behavior of power noise over various operational modes. To facilitate long system-level simulation with complex package and PCBs, chip power models are reduced into a compact, SPICE format; compatible with any simulation environment.


Chip power models represent the switching noise and parasitic network of the die.
The next generation of chip power model has recently become available, enabling more advanced CPS analysis methodologies. Designers are now able to probe at lower metal layer nodes in the die, to observe transistor-level noise in CPS simulation. The transient behavior of the die can now capture advanced operational modes, which are of particular interest to system engineers, such as resonance-inducing activity and transitions from low-power to high-power modes. Chip designers can now create user-configurable chip power models that can be programmed to represent different modes, depending on the simulation.

With the increased adoption of chip modeling, we can expect to see continued improvement of CPS co-design methodologies.

–Matt Elmore is a principal applications engineer for chip, package, system modeling and analysis at Apache Design Solutions.

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