What is CPS?

Silo-based designs are founded on over-design for margins. That doesn’t work anymore.


CPS stands for Chip-Package-System. It represents a paradigm shift from the old partitioned approach of IC design into a cohesive methodology that considers the ecology of the system as comprised of the chip, package and board.

Today’s design requirements are calling for a revisit to the way we look at IC design and validation. Companies no longer can afford to view design with a silo-based paradigm, where the chip, package and board process as independent projects. Silo-based approaches are founded on over-design for margins.

Look at today’s smartphones. The technology in these palm-sized devices runs several applications, lasts for hours on battery supply, and takes up less space than most wallets. With intense demands on power, performance, and regulatory specifications, it becomes necessary to view the chip, package, and board as a cohesive network of interdependent parts. In order to meet these kinds of requirements, designers are turning towards advanced modeling technologies and performing CPS validation.


In every area of sign-off validation, especially as we delve into deeper technologies, the electrical properties of the chip, package, and PCB are affecting each other in greater ways. Take for example, power integrity analysis. Increased demands on reducing cost are requiring designers to reduce package and PCB layers while maintaining functionally at the expense of increased impedance. Chip operational voltage depends on the on-die power delivery network and the switching characteristics of the die (di/dt), but is also heavily impacted by the impedance properties of the package and PCB. Designers are now using package and board models in their dynamic voltage drop simulations in order to improve sign-off accuracy.

EMI/EMC analysis is another area that the CPS paradigm has enabled a higher level of understanding. Recently, several of our industry’s high profile system failures have been traced back to EMI/EMC effects. The switching of on-die transistors creates an EMI signature, which then radiates through the package and out the PCB. In order to solve the problem of EMI, it becomes necessary to view the CPS analysis as whole. Modeling the chip as a source of radiation is just as important as the package and PCB medium that the radiation travels through.

With the increased proliferation of electronics in our lives and in the automobiles we drive, EMI has become a hot topic in CPS analysis. Interest has sparked, fueled by recent concerns with automotive reliability induced from the EMI generated by on-board electronics. EMI must be modeled and studied in order to ensure that electronic devices not only meet regulatory guidelines, but are not also causing self-inflicted failures.

At DesignCon 2011, the industry’s experts in CPS convergence will come together to discuss a complete system-wide approach to EMI in a workshop entitled “Methodologies for Chip-Package-System Co-design with EMI/EMC Focus.” The workshop will host presentations by experts at Infineon, LSI, and MST on methodologies and technologies for CPS and EMI/EMC modeling and analysis, including case studies and real design examples. Hope to see you there.

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