June 2013 - Page 6 of 6 - Semiconductor Engineering

Executive Briefing: Formal Attire

By Ed Sperling - 06 Jun, 2013 - Comments: 0

Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Low-e Windows Built Using The Design Rules

By Michael Watts - 06 Jun, 2013 - Comments: 0

By Michael P. C. Watts Last week I identified the four energy bands that determined the effectiveness of windows: visible, solar near IR, re-radiated mid IR and thermal convection. Each energy band requires its own mitigation strategy, dictated by the available materials. This week I will describe how to create low e windows using design rules for each energy band. The whole story is available... » read more

Scaling The Lowly SRAM

By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design

By Ed Sperling - 04 Jun, 2013 - Comments: 0

Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

Experts At The Table: Power Budgeting

By Ed Sperling - 03 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

RTL Signoff

By Ed Sperling - 03 Jun, 2013 - Comments: 0

Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

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