September 2016 - Page 4 of 11 - Semiconductor Engineering

The Week In Review: IoT
By Jeff Dorsch - 23 Sep, 2016 - Comments: 0

Security The Industrial Internet Consortium this week unveiled the Industrial Internet Security Framework, a set of specifications for connected health-care devices and hospitals, intelligent transportation, smart electrical grids, smart factories, and other cyber-physical systems in the Internet of Things. AT&T, Fujitsu, Hitachi, Infineon Technologies, Intel, Microsoft, and Symantec are among... » read more

450mm And Other Emergency Measures
By Ed Sperling - 22 Sep, 2016 - Comments: 0

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

5 Takeaways From BACUS
By Mark LaPedus - 22 Sep, 2016 - Comments: 0

As usual, the recent SPIE Photomask Technology Conference, sometimes called BACUS, was a busy event. The event, which took place in San Jose, Calif., featured presentations on the usual subjects in the photomask sector. There were presentations on mask writers, inspection, metrology, repair and cleaning. And, of course, the papers included masks based on extreme ultraviolet (EUV) lithography... » read more

Grappling With Manufacturing Data
By Ed Sperling - 22 Sep, 2016 - Comments: 2

As complexity goes up with each new process node, so does the amount of data that is generated, from initial GDSII to photomasks, manufacturing, yield and post-silicon validation. But what happens to that data, and what gets shared, remain a point of contention among companies across the semiconductor ecosystem. The problem is that to speed up the entire design through manufacturing process,... » read more

Will III-V Power Devices Happen?
By Ben Lee - 22 Sep, 2016 - Comments: 0

In a previous blog post, I provided a review of the overall power device market and trends driving changes in device evolution that entail materials innovation. For the industry to make such a shift, the advantages over mature, low-cost silicon technologies must be compelling and something the industry absolutely has to implement. Now I’d like to focus on new materials offering competitive be... » read more

The Pitfalls Of Auto-Stitching In Double-Patterning
By David Abercrombie - 22 Sep, 2016 - Comments: 0

Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Design Process Technology Co-Optimization For Manufacturability
By Dalong Zhao - 22 Sep, 2016 - Comments: 0

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

Mask Maker Worries Grow
By Mark LaPedus - 22 Sep, 2016 - Comments: 0

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Sorting Out Next-Gen Memory
By Mark LaPedus - 22 Sep, 2016 - Comments: 8

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Deploying Multi-Beam Mask Writers
By Mark LaPedus - 22 Sep, 2016 - Comments: 3

Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss the company’s deal with Intel, photomasks, multi-beam mask writer technology and other topics. What follows are excerpts of that conversation. SE: This has been a significant year for IMS for two reasons. First, Intel recently announced plans to acquire IMS. Second, at the recent ... » read more

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