Most experts thought the design industry moved beyond gate-level simulation. They were wrong.
The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late.
According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detailed checking all the way through the design flow is still going to be needed, including RTL simulation and even gate-level simulation.
Along those lines, gate level simulation—depending on the power architecture or the asynchronous nature of some of the designs that people are needing to cope with—is getting renewed attention.
“A lot of people were leaving gate-level simulation maybe as a final check and doing everything statically using formal verification, equivalence checking, etc. And we are seeing a little bit of a resurgence at gate-level driven by the need to take a much more detailed look at the dynamic effects of switching power domains,” he said.
There absolutely needs to be power-aware formal verification that is checking the design statically but in addition to that, especially where there are asynchronous effects that are difficult to verify formally, you need dynamic simulation and we are seeing a resurgence in gate-level simulation, Hardee explained.
As such, driven by low-power designs, Cadence at least is seeing an increase in gate-level simulation and not at the expense of formal verification.
In a small sense, what’s old is new.
~Ann Steffora Mutschler
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