Author's Latest Posts

DO-254: Increasing Verification Coverage By Test
By Aldec - 21 Mar, 2018 - Comments: 0

Verification coverage by test is essential to satisfying both the objectives of DO-254 and interpretation in FAA Oder 8110.105. However, verification of requirements by test during final board testing is challenging and time-consuming in most cases. This white paper explains the reasons behind these challenges and provides recommendations for how to overcome them. The recommendations center ... » read more

Partitioning Challenges In Multi-FPGA Prototyping
By Aldec - 21 Feb, 2018 - Comments: 0

Multi-FPGA prototyping of ASIC & SoC designs enables the highest clock rates among emulation techniques. However, design setup for prototyping is much more complicated and challenging. In this White Paper we uncover the common challenges of partitioning design to multiple FPGAs and provide solutions that will improve your prototype quality and shorten time spent on design setup. To read ... » read more

Achieving RTL-To-Netlist Equivalence
By Aldec - 30 Jan, 2018 - Comments: 0

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

Synthesis Of Energy-Efficient FSMs Implemented In PLD Circuits
By Aldec - 27 Sep, 2017 - Comments: 0

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous ci... » read more

Building And Configuring A Linux OS From Linaro
By Aldec - 25 Jan, 2017 - Comments: 0

The Linux operating system is a very popular operating system for embedded applications. Many modern systems including IoT gateways use the Linux OS because of its versatility and support for multiple architectures. The Aldec TySOM platform, which is based on the Xilinx Zynq SoC with ARM Cortex processor, can be utilized as an IoT Gateway system. This document describes the process for building... » read more

FPGA VHDL Verification
By Aldec - 22 Dec, 2016 - Comments: 0

By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more

Xilinx Zynq-based Development Platform for ADAS
By Aldec - 26 Oct, 2016 - Comments: 0

ADAS is an essential step between initial DA (Driver Assistance) systems and fully autonomous cars capable of driving without human guidance. Aldec provides an FPGA-based development platform powered by Xilinx Zynq-7000 SoC/FPGA heterogeneous technology, as well as a set of ADAS-class reference designs for rapid development of current and next-generation ADAS solutions for the automotive market... » read more

Introduction To AXI Protocol
By Aldec - 29 Sep, 2016 - Comments: 0

By Brandon Wade When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you ar... » read more

It’s Time To Get Your University In Sync With Zynq
By Aldec - 25 Aug, 2016 - Comments: 0

By Zach Nelson It’s time for universities to say goodbye to their outdated FPGA boards and introduce the Xilinx Zynq chip. The chip is a device which combines an FPGA fabric with a processing unit. The chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities. What can Zynq do? The Zynq ... » read more

Enhancing Verilog Designs With Embedded PSL
By Aldec - 26 Jul, 2016 - Comments: 0

PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design beh... » read more

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