Author's Latest Posts

SoC Verification Made Easy With Aldec HES-DVM

By Aldec - 23 Sep, 2015 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document... » read more

Introduction To DO-254

By Aldec - 26 Aug, 2015 - Comments: 0

For almost two decades, avionics system manufacturers have only had to adhere to DO-178 for the development of airborne software. RTCA/DO-178A was recognized by the Federal Aviation Administration (FAA) in 1985 for the development of airborne software, but RTCA/DO-254 was only recognized by the FAA in 2005 for the development of airborne electronic hardware (AEH). Developers of AEH are now face... » read more

Accelerate SoC Simulation Time Of Newer Generation FPGAs

By Aldec - 29 Jul, 2015 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. To read more, click here. » read more

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