Author's Latest Posts


Universal Verification Methodology Running Out Of Steam


For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

EDA On Board With New Package Options


A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

DAC 2020 Day One


DAC 2020 is like no other Design Automation Conference. It is virtual for this year — and hopefully only this year. The COVID pandemic has proven that face-to-face meetings and conferences are invaluable for many reasons. But with none of the distractions of a traditional conference, focusing on the content was easy. And because the sessions have been pre-recorded, the speakers for each se... » read more

Why Safety-Critical Verification Is So Difficult


The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Power Impact At The Physical Layer Causes Downstream Effects


Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Variables Complicate Safety-Critical Device Verification


The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Over-Design, Under-Design Impacts Verification


Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

New Approaches For Dealing With Thermal Problems


New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Data Strategy Shifting Again In Cars


Carmakers are modifying their data processing strategies to include more processing at or near the source of data, reducing the amount of data that needs to be moved around within a vehicle to both improve response time and free up compute resources. These moves are a world away from the initial idea that terabytes of streaming data would be processed in the cloud and sent back to the vehicl... » read more

The Increasingly Ordinary Task Of Verifying RISC-V


As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this... » read more

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