Author's Latest Posts

How To Fix Common Power Problems

As the industry moves to ever more advanced technology nodes, managing power has emerged as a primary challenge in modern SoC design. With smaller nodes, the wires become taller and narrower, which increases the resistivity and leads to more pronounced voltage drop effects. Electro-migration effects are also more severe at advanced nodes, causing serious reliability concerns. Both RTL synthesis... » read more

Leakage Optimization

By Arvind Narayanan For consumer electronics such as cell phones, tablets, and laptops, long battery life is a key requirement. Battery life is directly related to total power consumption—which is a function of switching activity, capacitance, and voltage—across all operational modes. In full active mode on a cell phone, for example, the dynamic power that comes from signal switching is hi... » read more

Guidelines For Designing Multi-Voltage ICs

By Arvind Narayanan Multi-voltage designs are increasingly common in ICs for mobile devices, but can be difficult to implement. The design flows for multi-voltage architectures are inherently complex and present many new challenges because many blocks are either operating at different voltages or are shut down intermittently. Multi-threshold CMOS switches enable switching off certain portio... » read more

The Trouble With Clock Trees

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more