Barry Pangrle

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Barry Pangrle is a power architect. He is based in Silicon Valley.

Author's Latest Posts

Intel’s Hot New Tri-Gate Processors
By Barry Pangrle - 10 May, 2012 - Comments: 0

By Barry Pangrle Intel announced its newest third-generation Core processors on April 23rd. There has been much anticipation surrounding these new chips from Intel, largely because of their new 22nm tri-gate process technology used to fabricate these devices. Figure 1, from the presentation entitled, “Intel’s Revolutionary 22nm Transistor Technology,” by Mark Bohr and Kaizad Mistry, s... » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

Intel vs. AMD: Who’s Right?
By Barry Pangrle - 08 Mar, 2012 - Comments: 0

By Barry Pangrle It’s all about the system. One energy-efficient component doesn’t an energy-efficient system make. There were two big announcements recently made by the industry’s two x86 designers. One was by Intel announcing its new Sandy Bridge Xeon Processor E5-2600 product family, and the other one was by AMD announcing its planned acquisition of SeaMicro. Both of these announce... » read more

A Brief History Of Power Formats
By Barry Pangrle - 09 Feb, 2012 - Comments: 0

Barry Pangrle A lot has happened in the industry in the way of power format standards over the past seven years. I’m going to attempt to hit on some of the highlights over that time period, especially with regards to the “Big 3” EDA vendors to hopefully put it all into better context for our readers. Early on, circa 2005, Mentor Graphics was working on a power format referred to as th... » read more

Undervolting & Underclocking
By Barry Pangrle - 12 Jan, 2012 - Comments: 0

By Barry Pangrle Last month we looked at record-breaking clock frequencies accompanied by voltage levels over 2V for some high-speed x86 processors. This month we’re going to go in the opposite direction—reducing the voltage and clock frequency to reduce power. Our processor of choice is the AMD A8-3850, a 100W, 2.9 GHz, quad-core, x86 processor that also incorporates 400 “Radeon core... » read more

Speed Demons
By Barry Pangrle - 01 Dec, 2011 - Comments: 0

By Barry Pangrle For extreme world record performance levels, the required power levels are also typically extreme. It’s that age-old battle against diminishing returns to squeeze out every last drop of performance versus practical limits and wallets. For example, a top fuel dragster can consume about six gallons of fuel for a quarter-mile run down the strip. As has previously been shown ... » read more

Innovation At The Core
By Barry Pangrle - 03 Nov, 2011 - Comments: 0

By Barry Pangrle A number of next-generation ARM-based multi-core systems are starting to show up in the press. Nvidia has released information on its upcoming Tegra 3 (also known as “Kal El”). At last week’s ARM Techcon in Santa Clara, ARM gave several presentations around its Cortex-A7 (Kingfisher) and Cortex-A15 (Eagle) architectures and collectively about its big.LITTLE strategy. Qua... » read more

Intel’s Claremont Near-Threshold Voltage IA Core
By Barry Pangrle - 06 Oct, 2011 - Comments: 0

By Barry Pangrle Intel announced many new technologies at its recent Intel Developer Forum (IDF) held from Sept. 13-15 in San Francisco, but the one announcement that jumped out at me was the unveiling of its work on a near-threshold voltage (NTV) processor named “Claremont.” For this exercise, Intel chose an older Pentium design to help minimize the number of variables the engineers would... » read more

Interconnect Power II
By Barry Pangrle - 08 Sep, 2011 - Comments: 0

Barry Pangrle After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative micropr... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

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