FinFET Vs. Tri-Gate

All FETs are not created equal, but the benefits of each have yet to be proven.


By Barry Pangrle
A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS are better than Intel’s. A number of things struck me as being interesting about this statement, but the foremost was that Intel would likely claim it isn’t even using FinFETs. Its new technology uses “Tri-Gate” transistors. So, you may be asking yourself, what’s the difference? In a paper authored by Robert Chau and others at Intel, they discussed different types of CMOS transistors and included a diagram similar to the one below.


The device in (a) is representative of a FinFET while (b) is representative of a Tri-Gate FET and (c) is a planar FET device. The FinFET includes a spacer at the top of the fin and is considered a dual-gated device with a gate on two sides of the channel. The Tri-Gate FET, on the other hand, is gated on three sides of the channel and hence the name “Tri-Gate.” The authors claimed that the Tri-Gate requirements were the most relaxed and allowed for improved manufacturability. I wrote a blog briefly discussing Intel’s Tri-Gate technology here.

I also wrote a blog about the SEMICON West panel session on FETs discussing different FET devices and mentioned the overview presentation on FinFETs given by Serge Biesemans of IMEC. One of the points made in Serge’s presentation is that there are a host of new device architectures that are aimed at fully depleted channels for better short-channel control (with FinFETs just being one of them). Serge also pointed out in his presentation that as fins get thinner, there is less control over the threshold voltage (Vt) of the devices. Another way to control the threshold voltage though is through work-function tuning of the metal gate process. This would seem to imply the need for the availability of multiple work-function gate types in order to provide a multi-Vt solution and along with it, additional process steps to manufacture the devices.

So, this brings us back to Subramani “Subi” Kengeri’s claim that GlobalFoundries has a better FinFET process for mobile SoCs. As was mentioned last summer at the SEMICON West conference panel, mobile SoC designers have become reliant upon multi-Vt processes to help produce better energy-efficient designs. The ability to choose between cells built with different threshold-voltage level transistors allows designers to optimize performance and power by using slower and less leaky transistors off of the critical paths. Some questions that will need to be answered before Subi’s claim can be verified are: 1) How much control is available over the threshold voltages; 2) What if any impact is there on process variation (i.e. how tightly controlled is the Vt process); 3) How much impact is there over the leakage of a FinFET by changing its threshold voltage, and 4) What additional complexities does this bring to the manufacturing process and what if any impact is there on yields?

If GlobablFoundries can produce a highly manufacturable multi-Vt process that still gives designers another knob for controlling power, this could be a real benefit for both them and their customers. Given that 28nm is the most recent technology node put into production at GlobalFoundries, we will have some time to wait before we know for sure.

–Barry Pangrle is a solutions architect for low power design and verification at Mentor Graphics.

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