Intel’s New Machine

The introduction of FinFETs well ahead of schedule raises the stakes for Intel’s competitors.

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By Barry Pangrle
Power is one of those product characteristics that touches on every phase of the design and verification process all the way from the system architecture down to the fabrication process used for the actual IC implementation. In this month’s blog we take a look at process technology and in this case, it appears to be the case that the technology rich are getting richer.

On May 4, 2011 Intel announced that their next generation “Ivy Bridge” processor will be built using 22nm 3D tri-gate transistors (also commonly referred to as FinFETs). These transistors will also continue the use of high-k metal gates (HKMG), so the new process adds onto the proven HKMG process capabilities already demonstrated by Intel. In their presentation entitled “Intel’s Revolutionary 22nm Transistor Technology”, Mark Bohr and Kaizad Mistry include the following diagram shown below in Figure 1.

 

Figure 1. Transistor Gate Delay

Figure 1. Transistor Gate Delay

The diagram shows that the 22nm tri-gate process can deliver the same gate delay as the 32nm planar process with a 0.2 V reduction in the operating voltage. At the “fast” end of the curve shown above, that looks like approximately a reduction from 1.0 V to 0.8 V, which from a first-order standpoint should be good for a 36% decrease in active power. If we look at the other end of the spectrum it looks like we get approximately a reduction from 0.8V to 0.6V, or roughly a 44% decrease in active power. Bohr and Mistry claim a >50% reduction in active power with good performance. Taking into account that there are additional effects on the power based on the technology, their claims appear completely plausible and quite outstanding.

I’ve included some diagrams for SoC consumer portable power trends from the 2008 Update, 2009, and 2010 Update ITRS Reports to help put this into better context. I’ve used these diagrams in a number of presentations to help illustrate the trend in power going forward. I’m often asked about the two dips that occur in 2014 and 2019. In the 2008 Update, there is a push-out of the metrics for FDSOI (Fully Depleted Silicon on Insulator) and MG (Multi-Gate) and an extension of the metrics for bulk planar devices. The start of the metrics for FDSOI is listed as 2013 and MG as 2015 and the real noticeable impacts to the diagrams appear to show up in 2014 and 2019. The basic shape of the plots remains relatively similar through all three reports. (One really noticeable change is in the Y-axis of the plots where the top of the charts are labeled at 3.5 W, 14.0 W, and 8.0 W respectively.) Essentially what Intel has announced is that it will be shipping production parts by early 2012 using a MG process. This is well ahead of the ITRS roadmap.

Figure 2. SoC Consumer Portable Power Trend [Source: ITRS, 2008 Update

Figure 2. SoC Consumer Portable Power Trend [Source: ITRS, 2008 Update

Figure 3. SoC Consumer Portable Power Trend [Source: ITRS, 2009

Figure 3. SoC Consumer Portable Power Trend [Source: ITRS, 2009

Figure 4. SoC Consumer Portable Power Trend [Source: ITRS, 2010 Update

Figure 4. SoC Consumer Portable Power Trend [Source: ITRS, 2010 Update

 

The reaction in the press to the announcement has been interesting, notably with the implications that this could have in the market place with regard to the ability to compete with ARM processors for low-power applications. For readers who have been following the trends in power efficiency, they’ve heard a lot about the importance of the front-end or architectural part of the design process in terms of creating efficient implementations. That continues to hold true here, as well. But one thing is clear—the designers that will be using Intel’s new P1270 process appear to have a great technology process to build upon.

–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.