AMD’s Bobcat Processor

A rare glimpse at the data provides great insights into low-power, energy-efficient design and some of the tradeoffs being made.


Barry Pangrle
The International Symposium on Low Power Electronics and Design (ISLPED) was held last week in Redondo Beach, California. There were many good presentations and keynote addresses and a topic that’s near to my heart, near-threshold voltage computing, was often discussed along with how best to (or not) handle variability.

One paper out of many that caught my attention was The Core-C6 (CC6) Sleep State of the AMD Bobcat x86 Microprocessor, by Aaron Rogers, David Kaplan, Eric Quinnell & Bill Kwan. What was notable about this paper was the publication of power and performance data for the processor. Since the “Bobcat” core is about to be replaced by the “Jaguar” core, AMD has allowed its engineers to publish some of the data regarding the older 40nm TSMC bulk CMOS design. Figure 1 below shows a die photo of the Ontario SoC that not only includes 2 Bobcat cores and cache (left side of figure), but significant GPU and other capabilities, as well.

Figure 1. De-processed die photo of 40 nm Ontario SoC. Source: AMD

Figure 2 below shows a graph of the dynamic power for one core operating at 90°C and at various frequency and voltage points. For people interested in creating higher-level power models to approximate processors running at different operating points, these graphs should be of interest.

Figure 2. Power vs. Voltage. Source: AMD

Figure 3. Power vs. Voltage. Data Source: AMD

Figure 3 shows the best and worst case points presented across 5 different operating frequencies for the core. It’s interesting to note that there appears to be about a factor of 2 power increase in the worst case compared to the best case listed.

Figure 4. Power vs. Clock Frequency. Data Source: AMD

Given the data, I couldn’t help but play around to see what else I could possibly try to glean from it. Figure 4 shows some plots for power versus clock frequency for given voltage levels. For less than 2 points at any voltage, I left the data off of this plot for clarity (and even only two points makes for a really nice straight line). For dynamic power, we’d expect that the power would increase linearly with clock frequency at a constant voltage, and the plotted data in Figure 4 seems to bear this out. The only slightly odd point is the jump at 1700 MHz for 1.1 V, which can also be seen back on Figure 2.

All in all though, these plots look like fairly straight lines. So if the dynamic power seems to be tracking linearly with the clock frequency (as expected), we might guess that we should also be able to factor in a voltage squared term to make a predictive model. Figure 5 below shows plots for the predicted dynamic power levels starting with a base at the 500 MHz point and then factoring in the voltage squared component and linear component for the increase in clock frequency.

Figure 5. Predicted Power vs. Voltage. Data Source: AMD

The predictive models for the best-case and worst-case curves are not too bad. The worst-case curve was surprisingly close, in my opinion.

The authors go into some depth about the static power component and their sleep mechanism for reducing static power (actually the majority of the paper). Thanks to AMD for making this information available to the low-power community and I’d like to encourage anyone who is interested in low-power/energy-efficient design to check out the conference proceedings.

—Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.