Bryon Moyer

  (all posts)
Bryon Moyer is a technology editor at Semiconductor Engineering.

Author's Latest Posts

5G Brings New Testing Challenges
By Bryon Moyer - 11 Aug, 2020 - Comments: 0

As 5G nears commercial reality, makers of chips and systems that will support 5G will need to take on the standard burden of characterizing and testing their systems to ensure both performance and regulatory adherence. Millimeter-wave (mmWave) and beamforming capabilities present the biggest testing challenges. “5G is expected to have the extended coverage plus the bandwidth to harness ... » read more

WiFi Evolves For The IoT
By Bryon Moyer - 06 Aug, 2020 - Comments: 0

WiFi is everywhere, and it’s the most prevalent of the communication protocols that use unlicensed spectrum. But as a common protocol for the Internet of Things (IoT), it faces challenges both because of congestion and the amount of energy it consumes. Two new approaches aim to address those concerns. One is to use multiple channels at once. The second involves the new 802.11ah HaLow stand... » read more

What’s After 5G
By Bryon Moyer - 20 Jul, 2020 - Comments: 1

This year’s IEEE Symposia on VLSI Technology and Circuits (VLSI 2020) included a presentation by NTT Docomo that looked far into the future of cellular communications, setting the stage for a broad industry shift in communication. This is far from trivial. 5G only just recently entered the commercial world, and — especially with the higher millimeter-wave (mmWave) frequencies — it has ... » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Are Better Machine Training Approaches Ahead?
By Bryon Moyer - 01 Jul, 2020 - Comments: 1

We live in a time of unparalleled use of machine learning (ML), but it relies on one approach to training the models that are implemented in artificial neural networks (ANNs) — so named because they’re not neuromorphic. But other training approaches, some of which are more biomimetic than others, are being developed. The big question remains whether any of them will become commercially viab... » read more

ML Opening New Doors For FPGAs
By Bryon Moyer - 24 Jun, 2020 - Comments: 0

FPGAs have long been used in the early stages of any new digital technology, given their utility for prototyping and rapid evolution. But with machine learning, FPGAs are showing benefits beyond those of more conventional solutions. This opens up a hot new market for FPGAs, which traditionally have been hard to sustain in high-volume production due to pricing, and hard to use for battery-dri... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

ESD Requirements Are Changing
By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy