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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Can You Build A Known-Good Multi-Die System?
By Ed Sperling - 18 Jun, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadenc... » read more

LLMs On The Edge
By Ed Sperling - 16 Jun, 2025 - Comments: 0

Nearly all the data input for AI so far has been text, but that's about to change. In the future, that input likely will include video, voice, as well as other types of data, causing a massive increase in the amount of data that needs to be modeled and the compute resources necessary to make it all work. This is hard enough in hyperscale data centers, which are sprouting up everywhere to handle... » read more

Big Changes In Medical Electronics
By Ed Sperling - 09 Jun, 2025 - Comments: 0

Medical devices are becoming more capable, more complicated, and more deployable in the field rather than in a hospital or a doctor's office. But getting these purpose-built devices into the hands of consumers requires a whole bunch of new challenges, from safeguarding fragile on-board chemistries that can be destroyed by existing chip manufacturing and packaging processes to ensuring the mater... » read more

How Secure Are Analog Circuits?
By Ed Sperling - 05 Jun, 2025 - Comments: 0

The move toward multi-die assemblies and the increasing value of sensor data at the edge are beginning to focus attention and raise questions about security in analog circuits. In most SoC designs today, security is almost entirely a digital concern. Security requirements in digital circuits are well understood, particularly in large data centers and at the upper end of edge computing, which... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI
By Ed Sperling - 29 May, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Optical Interconnectivity At 224 Gbps
By Ed Sperling - 28 May, 2025 - Comments: 0

AI is generating so much traffic that traditional copper-based approaches for moving data inside a chip, between chips, and between systems, are running out of steam. Just adding more channels is no longer viable. It requires more power to drive signals, and the distance those signals can travel without excessive loss is shrinking. Mike Klempa, product marketing specialist at Alphawave Semi, di... » read more

Problems In Testing AI Chips
By Ed Sperling - 20 May, 2025 - Comments: 0

As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Speeding Up Die-To-Die Interconnectivity
By Ed Sperling - 14 May, 2025 - Comments: 0

Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks about how to speed up data movement between chiplets with bi-direction... » read more

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