Author's Latest Posts


Battling Over Shrinking Physical Margin In Chips


Smaller process nodes, coupled with a continual quest to add more features into designs, are forcing chipmakers and systems companies to choose which design and manufacturing groups have access to a shrinking pool of technology margin. In the past margin largely was split between the foundries, which imposed highly restrictive design rules (RDRs) to compensate for uncertainties in new proces... » read more

Using AI To Close Coverage Gaps


Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

RTL Restructuring Issues


Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

Challenges Of Heterogeneous Integration


Heterogeneous integration opens the door to an almost unlimited number of features in a single package, but it also adds system-level challenges into a small space filled with a whole spectrum of possible interactions. Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology, talks about a variety of issues ranging from uneven aging, warpage, and different mechanical stresse... » read more

EDA, IP Fundamentals Shift As Market Soars


EDA tools and IP continued their double-digit growth trajectory this year, despite a downturn in consumer electronics and a continued shortage of key components that took a large bite out of the semiconductor market as a whole. A just-released report from the ESD Alliance showed a 12% increase in revenue for Q1, increasing to $3.95 billion compared with $3.53 billion in the same period in 20... » read more

Changes In Memory Design


An explosion of data in automotive, cloud, and AI are altering the fundamentals of memory design. One size no longer fits all, as memory is used for a broader set of applications, from automotive and cloud to consumer devices. Anand Theruvengadam, director of product management at Synopsys, talks about the impact of big data applications on density, memory stacking, and growing concerns about r... » read more

Challenges Grow For Data Management And Sharing In EDA


Semiconductor Engineering sat down to talk about more openness in EDA data, how increased complexity is affecting time to working silicon, and the impact of geopolitics, with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business U... » read more

Preparing For 5G Millimeter Wave And 6G


Cellular technology is about to take a giant leap forward, but the packaging, assembly, and testing of the chips used in 5G millimeter wave and the forthcoming 6G ecosystem will be significantly more complicated than anything used in the past. So far, most 5G devices are still working at sub-6 GHz frequencies. A massive rollout of mmWave technology over the next few years will significantly ... » read more

The Next Chip Shortages?


The rollout of chiplets and heterogeneous designs could have unexpected implications on a global scale, creating a whole new round of chip shortages that will be much harder to fix. It's impossible to say for certain what will happen here in the wake of massive changes in chip design and a fluid and unpredictable geopolitical situation. The trade war between the United States and China began... » read more

CEO Outlook: Chiplets, Data Management, And Reliability


Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

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