Author's Latest Posts


Issues In Ramping Advanced Packaging


Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entir... » read more

How AI Will Impact Chip Design And Designers


Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

Changes In Scan Test Data


Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

Accelerating IP Reuse


Semiconductors are no longer monolithic designs developed by a single company. There is more third-party IP from different sources — as many as 1,000 different IPs in a complex SoC — and all of that needs to be integrated and work as one system, something that can require a lot of effort and time. Insaf Meliane, product management and marketing director at Arteris, talks about how the new v... » read more

AI In The IC Equipment Ecosystem


AI is playing an increasingly critical role in improving semiconductor equipment and processes, which are necessary as the industry moves to advanced manufacturing processes. This requires more steps, tighter integration and analysis of those various steps, and better optimization of tools. David Fried, corporate vice president at Lam Research, talks about how to accelerate the development of A... » read more

Crisis Ahead: Power Consumption In AI Data Centers


AI data centers are consuming energy at roughly four times the rate that more electricity is being added to grids, setting the stage for fundamental shifts in where power is generated, where AI data centers are built, and much more efficient system, chip, and software architectures. The numbers are particularly striking for the United States and China, which are in a race to ramp up AI data ... » read more

Silent Data Corruption


Everyone expects their compute systems to generate the correct answer. When they don't, it's cause for alarm, because it's not always clear how long the problem has persisted. Even worse, chips and systems are now so complex that it may require a unique sequence of operations to trigger a silent data error, and they may show up only occasionally, and maybe only after months or years of use in t... » read more

AI In Chip Design: Tight Control Required


Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Silicon IP Revenue Spikes


EDA and silicon IP revenue grew 12.8% in Q1 2025, totaling $5.098 billion compared to $4.522 billion in the same period last year, but the real story was on the IP side, surging 29.6% year-over-year to $1.577 billion. Drilling deeper into those numbers, revenue for non-reporting IP companies — predominantly Arm — jumped 34.1% YoY to $1.031 billion. That was positive news for the IP marke... » read more

Rethinking Scan Chains In Semiconductor Test


An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D'Souza, technical product director for yield learning products in Siemens E... » read more

← Older posts Newer posts →