Can A Computer Science Student Be Taught To Design Hardware?
To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.
Advanced Packaging Limits Come Into Focus
Mechanical and process control limits are now shaping what can be manufactured at scale.
Startup Funding: Q1 2026
Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.
All AI Data Center Interconnects Will Be Optical Within 5 Years
InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).
Making Hybrid Bonding Better
Why this technology is so essential for multi-die assemblies, and how it can be improved.
When Semiconductor Materials Misbehave
The gap between lab performance and fab reality is growing wider as packages grow more complex.
Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.
The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
Leave a Reply