Author's Latest Posts


More Multiply-Accumulate Operations Everywhere


Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

PCIe 5.0 Drill-Down


Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

What’s Changing, What Isn’t


The global pandemic is creating economic chaos on a global scale. The big question now is when the coronavirus is brought under control, and just how long its effects will extend beyond the current health crisis. For the semiconductor industry, which has weathered many long and deep financial swings, this one at least is finite. When the virus stops spreading, or when treatments are availabl... » read more

Building A Safety Verification Flow


Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Speeding Up Verification Using SystemC


Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Is It Time To Decentralize The Supply Chain?


One of the key requirements in any engineered system is a backup plan. A single point of failure in safety-critical or mission-critical applications can lead to disaster, whether that involves a smart phone, a car, a bridge, an airplane, or a design, manufacturing or business process. So why has this been largely ignored across the semiconductor manufacturing supply chain? The answer is comp... » read more

The Ins And Outs Of Silicon Carbide


John Palmour, CTO at Cree, sat down with Semiconductor Engineering to talk about silicon carbide, how it compares to silicon, what's different from a design and packaging standpoint, and where it's being used. What follows are excerpts of that conversation. SE: SiC is well-understood in power electronics and RF, but is the main advantage the ability to run devices hotter than silicon, or is ... » read more

Timing Closure At 7/5nm


Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

How Much Power Will AI Chips Use?


AI and machine learning have voracious appetites when it comes to power. On the training side, they will fully utilize every available processing element in a highly parallelized array of processors and accelerators. And on the inferencing side they, will continue to optimize algorithms to maximize performance for whatever task a system is designed to do. But as with cars, mileage varies gre... » read more

Visualizing Differences In Analog Design


Prathna Sekar, technical account manager at ClioSoft, explains the challenges of managing analog versus digital IP, including how to deal with dozens or even hundreds of versions of a schematic, and why visualization is so important for identifying changes and updates to an analog design. » read more

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