Author's Latest Posts


Scaling At The Angstrom Level


It now appears likely that 2nm will happen, and possibly the next node or two beyond that. What isn't clear is what those chips will be used for, by whom, and what they ultimately will look like. The uncertainty isn't about the technical challenges. The semiconductor industry understands the implications of every step of the manufacturing process down to the sub-nanometer level, including ho... » read more

Big Changes In Tiny Interconnects


One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

Thinking Way, Way Outside The Box


The COVID-19 High Performance Computing Consortium has set records for global cooperation by giant companies, universities and various federal agencies and national laboratories. But it also may have cracked opened a door for much more than that. Until now, there has been a massive race for dominance in the data center. Big companies have gotten rich on data, building infrastructure at a col... » read more

Stream Vs. Pool Data Processing


Geoff Tate, CEO of Flex Logix, looks at the very different data processing requirements at the edge and in the data center, and what really drives efficiency and speed in applications such as automotive. » read more

Redefining Device Failures


Can a 5nm or 3nm chip really perform to spec over a couple decades? The answer is yes, but not using traditional approaches for designing, manufacturing or testing those chips. At the next few process nodes, all the workarounds and solutions that have been developed since 45nm don't necessarily apply. In the early finFET processes, for example, the new transistor structure provided a huge im... » read more

Last-Level Cache


Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

Lane Departure Warnings For The Auto Industry


The automotive chip market is undergoing a series of subtle but significant shifts behind the scenes that could have major implications for the global automotive supply chain. After a few years of racing toward autonomous vehicles and setting in motion a frenzy of activity, some of the big auto makers have begun taking the design of key functions such as centralized logic in-house. There... » read more

More Multiply-Accumulate Operations Everywhere


Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

PCIe 5.0 Drill-Down


Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

What’s Changing, What Isn’t


The global pandemic is creating economic chaos on a global scale. The big question now is when the coronavirus is brought under control, and just how long its effects will extend beyond the current health crisis. For the semiconductor industry, which has weathered many long and deep financial swings, this one at least is finite. When the virus stops spreading, or when treatments are availabl... » read more

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