Alternative Text

Ed Sperling

  (all posts)
Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Promises And Pitfalls Of SoC Restructuring
By Ed Sperling - 12 Jun, 2024 - Comments: 0

As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interface... » read more

Making Adaptive Test Work Better
By Ed Sperling - 10 Jun, 2024 - Comments: 0

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

MCU Changes At The Edge
By Ed Sperling - 03 Jun, 2024 - Comments: 0

Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ... » read more

Electromigration And IR Drop At Advanced Nodes
By Ed Sperling - 22 May, 2024 - Comments: 0

Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil... » read more

Adapting To Evolving IC Requirements
By Ed Sperling - 07 May, 2024 - Comments: 0

As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ... » read more

Sensor Fusion Challenges In Automotive
By Ed Sperling - 02 May, 2024 - Comments: 0

The number of sensors in automobiles is growing rapidly alongside new safety features and increasing levels of autonomy. The challenge is integrating them in a way that makes sense, because these sensors are optimized for different types of data, sometimes with different resolution requirements even for the same type of data, and frequently with very different latency, power consumption, and re... » read more

Overlay Optimization In Advanced IC Substrates
By Ed Sperling - 29 Apr, 2024 - Comments: 1

Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

EDA Looks Beyond Chips
By Ed Sperling - 25 Apr, 2024 - Comments: 0

Large EDA companies are looking at huge new opportunities that reach well beyond semiconductors, combining large-scale multi-physics simulations with methodologies and tools that were developed for chips. Top EDA executives have been talking about expanding into adjacent markets for more than a decade, but the broader markets were largely closed to them. In fact, the only significant step in... » read more

Secure Movement Of Data In Test
By Ed Sperling - 16 Apr, 2024 - Comments: 0

Historically, test data flowed out of the tester and was loaded into a file. But with heterogeneous integration, including chiplets and IP from multiple vendors, test data is now being streamed across the manufacturing floor where it can be used to make real-time decisions. Eli Roth, product manager for smart manufacturing at Teradyne, talks with Semiconductor Engineering about challenges in da... » read more

Challenges With Chiplets And Power Delivery
By Ed Sperling - 15 Apr, 2024 - Comments: 0

Chiplets hold the potential to deliver the same PPA benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy