Author's Latest Posts


Why Move To 2nm?


Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

Agentic AI In Chip Manufacturing


Agentic AI — breaking AI into individual agents that can work together and collaboratively — will be the real game changer for AI in chip manufacturing. By taking humans out of the loop, these agents can be programmed using natural language to automatically solve problems and improve efficiency. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks  about w... » read more

Software-Defined Systems


Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Big Changes Ahead For Semiconductor Manufacturing


John Kibarian, CEO of PDF Solutions, talks with Semiconductor Engineering's Ed Sperling about the growing role of AI in chip manufacturing, the impact of 3D-ICs on the supply chain, and how to shorten cycle time to get leading-edge chips and multi-die assemblies to market more quickly. To listen, click here.   » read more

Challenges In Moving Data In Chips


The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they're supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris... » read more

EDA and IP Revenue Up 8.8%


EDA and IP revenue grew 8.8% in Q3 2025 to $5.566 billion, up from $5.115 billion in the same period in 2024, according to new data from ESD Alliance. But beneath those respectable, if not spectacular numbers, some interesting shifts are underway. China returned to double-digit growth after several quarters of lackluster sales. But the biggest surprise was EDA/IP revenues from South Korea an... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Reliability And Traceability In Advanced Packages


The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

Generative AI In Chip Manufacturing


Generative AI is a natural-language or text-based query, predicting patterns based on a massive set of data. While most of the attention has been focused on chatbots and copilots, it also can be used to identify small, transient aberrations in semiconductor manufacturing that are otherwise difficult to find. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks ... » read more

DFT Shifts Further Left


Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

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