Author's Latest Posts


Challenges In Moving Data In Chips


The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they're supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris... » read more

EDA and IP Revenue Up 8.8%


EDA and IP revenue grew 8.8% in Q3 2025 to $5.566 billion, up from $5.115 billion in the same period in 2024, according to new data from ESD Alliance. But beneath those respectable, if not spectacular numbers, some interesting shifts are underway. China returned to double-digit growth after several quarters of lackluster sales. But the biggest surprise was EDA/IP revenues from South Korea an... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Reliability And Traceability In Advanced Packages


The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

Generative AI In Chip Manufacturing


Generative AI is a natural-language or text-based query, predicting patterns based on a massive set of data. While most of the attention has been focused on chatbots and copilots, it also can be used to identify small, transient aberrations in semiconductor manufacturing that are otherwise difficult to find. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks ... » read more

DFT Shifts Further Left


Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

Small Language Models Create New Security Risks


The rollout of edge AI is creating new security risks due to a mix of small language models (SLMs), their integration into increasingly complex hardware, and the behavior and interactions of both over time. AI data centers still garner the most attention due to massive investments and an ongoing flood of deals and acquisitions, but the edge is quietly starting to take shape for several reaso... » read more

AI-Driven Collaboration In Chip Manufacturing


3D chips and multi-die assemblies can offer significant improvements in performance and power, but the tradeoff is the increased amount of time and money it takes to generate working silicon. There are more process steps, more interactions between processes, and more data to manage throughout the manufacturing flow — so much, in fact, that it has now reached well beyond what even the best eng... » read more

Challenges In Testing Photonics In Chips


The semiconductor industry has spent decades improving reliability and consistency by standardizing when and how to test it, how to collect critical data from those tests, and what to do with that data. But electrical test data is very different from silicon photonics, which is being bundled into these SoCs and multi-die assemblies alongside traditional electrical components. Aftkhar Aslam, CEO... » read more

Changes In Mixed-Signal IC Verification


Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

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