AI-Driven Collaboration In Chip Manufacturing

By Ed Sperling - 24 Nov, 2025 - Comments: 0

3D chips and multi-die assemblies can offer significant improvements in performance and power, but the tradeoff is the increased amount of time and money it takes to generate working silicon. There are more process steps, more interactions between processes, and more data to manage throughout the manufacturing flow — so much, in fact, that it has now reached well beyond what even the best eng... » read more

Challenges In Testing Photonics In Chips

By Ed Sperling - 21 Nov, 2025 - Comments: 0

The semiconductor industry has spent decades improving reliability and consistency by standardizing when and how to test it, how to collect critical data from those tests, and what to do with that data. But electrical test data is very different from silicon photonics, which is being bundled into these SoCs and multi-die assemblies alongside traditional electrical components. Aftkhar Aslam, CEO... » read more

Changes In Mixed-Signal IC Verification

By Ed Sperling - 19 Nov, 2025 - Comments: 0

Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

Advanced Process Control In Semiconductor Manufacturing

By Ed Sperling - 14 Nov, 2025 - Comments: 0

Fifth in a seven-part series: Advanced process control for semiconductor wafers is evolving in ways that can significantly improve yield and reduce scrap. As dimensions shrink, the need to improve manufacturing processes and reduce variability requires more precision. "Classic" APC was a step in the right direction, identifying problems in a process chamber, for example, and automating adjustme... » read more

Improving IC System Quality And Performance

By Ed Sperling - 12 Nov, 2025 - Comments: 0

Ensuring that multi-die assemblies and advanced SoCs will work as expected from time zero to the end of their lifecycle adds new challenges for chipmakers and their customers. Chips are being run harder, hotter, and for longer periods of time, often in unique configurations and with customized workloads. Alex Burlak, vice president of test and analytics at proteanTecs, talks about how to identi... » read more

LPDDR6: Not Just For Mobile Anymore

By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

Small Vs. Large Language Models

By Ed Sperling - 03 Nov, 2025 - Comments: 0

The proliferation of edge AI will require fundamental changes in language models and chip architectures to make inferencing and learning outside of AI data centers a viable option. The initial goal for small language models (SLMs) — roughly 10 billion parameters or less, compared to more than a trillion parameters in the biggest LLMs — was to leverage them exclusively for inferencing. In... » read more

Critical Factors For Storing Data In DRAM

By Ed Sperling - 27 Oct, 2025 - Comments: 0

DRAM is becoming more complicated to develop, and more difficult to manage inside AI data centers. In the past, latency, bandwidth, and capacity were the primary considerations. But as the amount of data that needs to be processed, moved, and stored continues to rise, a whole new set of factors is emerging. Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load,... » read more

In-System Test For AI Data Centers

By Ed Sperling - 20 Oct, 2025 - Comments: 0

Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Using AI/ML To Find And Correlate IC Test Data

By Ed Sperling - 15 Oct, 2025 - Comments: 0

What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

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