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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Data Leakage In Heterogeneous Systems
By Ed Sperling - 02 Nov, 2023 - Comments: 0

Semiconductor Engineering sat down with Paul Chou, senior director of security architecture at NVIDIA, to discuss data leakage in heterogeneous designs. What follows are excerpts of that one-on-one interview, which was held in front of a live audience at the Hardwear.io conference. SE: We think about hardware in terms of a chip, but increasingly there is data moving through different systems... » read more

DSP Techniques For High-Speed SerDes
By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Heterogeneous Integration Finding Its Footing
By Ed Sperling - 19 Oct, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroianni, advanced packagin... » read more

Why Using Commercial Chiplets Is So Difficult
By Ed Sperling - 18 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts... » read more

Verifying A RISC-V Processor
By Ed Sperling - 17 Oct, 2023 - Comments: 0

Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardwa... » read more

EDA Revenue Up Again
By Ed Sperling - 17 Oct, 2023 - Comments: 0

The EDA industry reached $3.963 billion in revenue in Q2, boosted by a 17.6% increase in computer-aided engineering and a 17.2% increase in IP physical design and verification, according to a just-released ESD Alliance Electronic Market Data report. The overall growth was offset by an accounting change in the IP business, which resulted in a 11.6% decline to $1.255 billion, as well as some w... » read more

Issues In Calculating Glitch Power
By Ed Sperling - 11 Oct, 2023 - Comments: 0

The amount of power consumed by redundant non-functional toggles, or glitch power, can be as high as 35% of total power consumption in a design. What can be done about that? Godwin Maben, low-power architect and scientist at Synopsys, takes a deep dive into the causes of glitch, how it is affected by new process nodes and heterogeneous integration, and the impact of different workloads, higher ... » read more

Die-To-Die Security
By Ed Sperling - 02 Oct, 2023 - Comments: 0

Security concerns are growing as more chiplets or die are added into a package. There are more possible attack points, and data is becoming increasingly valuable, which makes a successful attack much more lucrative than in the past. Mike Borza, Synopsys scientist, talks about the impact of heterogeneous integration on security, what the risks are for multi-tenant data centers, and what happens ... » read more

Application-Optimized Processors
By Ed Sperling - 29 Sep, 2023 - Comments: 0

Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Data Management Challenges In Heterogeneous Systems
By Ed Sperling - 27 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss issues in smart manufacturing of chips, including data management, chiplets, and standards, with Mujtaba Hamid, general manager for product management for secure cloud environments at Microsoft; Vijaykishan Narayanan, vice president and general manager of India engineering and operations at proteanTecs; KT Moore, vice presiden... » read more

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